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V. Vartanian,
S. Zollner,
A.V.-Y. Thean,
T. White,
B.-Y. Nguyen,
L. Prabhu,
D. Eades,
S. Parsons,
H. Desjardins,
K. Kim, [......],
R. Powers,
G. Spencer,
N. Ramani,
M. Kottke,
M. Canonico,
X.-D. Wang,
L. Contreras,
D. Theodore,
R. Gregory,
S. Venkatesan
[show abstract]
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ABSTRACT: The semiconductor industry has maintained its historical exponential improvement in performance by aggressively scaling transistor dimensions. However, as devices approach sub-100-nm dimensions, scaling becomes more challenging and new materials are required to overcome the fundamental physical limitations imposed by existing materials. For example, as power supply voltages continue to decrease with successive scaling, enhancing carrier mobility using biaxially tensile-stressed Si on relaxed SiGe on SOI and on bulk substrates has become a viable option to sustain continual drive current increase without traditional scaling. Although the addition of strained-Si to conventional MOSFET devices is compatible with existing mainstream CMOS process technology, there are new device and process integration challenges, wafer quality monitoring demands, and stringent requirements for film morphology and strain uniformity, imposing new demands on material characterization. Material requirements for strained-Si CMOS devices include having uniform SiGe thickness, Ge composition, and strain distribution. These are required to maintain uniform device performance as well as low defect density for high minority carrier lifetimes and transconductance, as well as low surface roughness to minimize the impact of interface scattering on carrier mobilities. The parameters of interest in strained-Si CMOS technology include SiGe and Si channel thickness, Ge composition, strain, dislocation density, interface quality, and roughness. Nondestructive inline metrology techniques include spectroscopic ellipsometry for film thickness and Ge composition, X-ray reflectivity for thickness, density, and roughness measurements, X-ray fluorescence for Ge composition, UV-Raman spectroscopy for channel strain characterization, IR photoluminescence for defect detection, and X-ray diffraction for both Ge content and strain measurement. While most of these techniques are well established in the semiconductor -
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industry, some will require development for application to volume manufacturing. This paper will focus on various metrology approaches used in strained-Si CMOS devices
IEEE Transactions on Semiconductor Manufacturing 12/2006; · 0.72 Impact Factor
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A.V.-Y. Thean,
L. Prabhu, V. Vartanian,
M. Ramon,
B.-Y. Nguyen,
T. White,
H. Collard,
Q.-H. Xie,
S. Murphy,
J. Cheek,
S. Venkatesan,
J. Mogab,
C.H. Chang,
Y.H. Chiu,
H.C. Tuan,
Y.C. See,
M.S. Liang,
Y.C. Sun
[show abstract]
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ABSTRACT: This paper describes the novel stress engineering of SC-SSOI devices through the interactions between biaxial lattice strain, uniaxial relaxation, process-induced stressor and channel orientation. We have demonstrated a method of uniaxial stress relaxation with compressive capping layer (cESL) to achieve the desired stress configurations for enhanced short-channel SC-SSOIpMOS devices
Electron Devices Meeting, 2005. IEDM Technical Digest. IEEE International; 01/2006
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[show abstract]
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ABSTRACT: Tailoring the chemical environment in plasmas by addition of reactive gases to affect byproduct formation has been demonstrated to reduce perfluorocompound (PFC) emissions. Perfluorocompound emissions from dielectric etch processes are reduced by oxygen addition, which reduces polymerization and increases etch rates, primarily by affecting the fluorine or carbon in the plasma, and secondarily, by affecting resist erosion. Oxygen or water vapor introduced upstream of plasma abatement devices reduces PFC reformation by preferentially combining with carbon and fluorine-containing radicals to form thermodynamically favorable byproducts that are non- or low-global warming. Introducing oxygen to low-k chemical vapor deposition (CVD) chamber clean processes also reduces PFC emissions, primarily by reducing CF<sub>4</sub> by forming thermodynamically stable CO and CO<sub>2</sub>. Analogously, adjusting the fuel or the oxidizer flow in fuel-fired abatement devices provides a higher flame temperature where thermal cracking of higher molecular weight low-k CVD organosilicon precursors can more readily occur, allowing the carbon-rich precursors to more completely oxidize.
IEEE Transactions on Semiconductor Manufacturing 12/2004; · 0.72 Impact Factor
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Bich-Yen Nguyen,
A. Thean,
T. White,
A. Vandooren,
M. Sadaka,
L. Mathew,
A. Barr,
S. Thomas,
M. Zalava,
Da Zhang, [......],
S. Kalpat,
L. Prabhu,
V. Kaushik,
Y. Du,
T. Dao,
M. Mendicino,
M. Orlowski,
P. Tobin,
J. Mogab,
S. Venkatesan
[show abstract]
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ABSTRACT: In this paper, we will detail the issues with new materials being introduced into CMOS devices and present some potential solutions to enable high performance and low power CMOS for the 65nm node and beyond.
Integrated Circuit Design and Technology, 2004. ICICDT '04. International Conference on; 02/2004
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B.-Y. Nguyen,
S. Zhang,
A. Thean,
P. Grudowski, V. Vartanian,
T. White,
S. Zollner,
D. Theodore,
B. Goolsby,
H. Desjardins, [......],
P. Montgomery,
C. Parker,
J. Hildreth,
R. Noble,
M. Jahanbani,
D. Eades,
J. Cheek,
B. White,
J. Mogab,
S. Venkatesan
[show abstract]
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ABSTRACT: Uniaxial stressors have been mainly employed for boosting PMOS performance, while it is more difficult to increase NMOS performance using tensile stressors. This results in changing the n:p ratio, which requires circuit layout changes. Enhancing both NMOS and PMOS performance to retain the same n:p ratio is desirable. Interactions between biaxial lattice strain, uniaxial relaxation, process-induced stressor and channel orientation have been optimized to achieve the desired stress configurations for enhancing both short-channel SSOI NMOS and PMOS devices
SiGe Technology and Device Meeting, 2006. ISTDM 2006. Third International;
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A.V.-Y. Thean,
D. Zhang, V. Vartanian,
V. Adams,
J. Conner,
M. Canonico,
H. Desjardin,
P. Grudowski,
B. Gu,
Z.-H. Shi, [......],
S. Backer,
L.-B. La,
D. Burnett,
T. White,
B.-Y. Nguyen,
B.E. White,
S. Venkatesan,
J. Mogab,
I. Cayrefourcq,
C. Mazure
[show abstract]
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ABSTRACT: This paper describes a biaxial-uniaxial hybridized strained CMOS technology achieved through selective uniaxial relaxation of thick SSOI, dual-stress nitride capping layer, and embedded SiGe source/drain. Through novel strain engineering, nFET/pFET Idsat enhancements as high as 27%/36% have been achieved for sub-40nm devices at 1V with 30% reduction in gate leakage current, while introducing minimum process complexity. This work demonstrates the scalability of SC-SSOI and its advantages over pure biaxial and single uniaxial strained Si technologies
VLSI Technology, 2006. Digest of Technical Papers. 2006 Symposium on;
