G.S. La Rue

Publications (12)8.36 Total impact

• Article: A 12-Bit Nonlinear DAC for Direct Digital Frequency Synthesis

  Zhihe Zhou, G.S. La Rue
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  ABSTRACT: A 12-bit nonlinear digital-to-analog converter (DAC) was fabricated in a 0.35-mum SOI CMOS process. The nonlinear DAC can implement a piecewise-linear approximation to a sine function and results in significant reduction of complexity and power dissipation when used in direct digital frequency synthesizers (DDFSs). The DDFS look-up table only needs to store offset and gain values for each segment. The look-up table size can be reduced from 11K bits to 544 bits for a 12-bit DDFS with 72 dB spurious-free dynamic range (SFDR). The nonlinear DAC consists of a 12-bit binary-weighted offset DAC and a multiplying DAC. The DACs use a current steering architecture for high-speed operation and the 5 most significant bits of the offset DAC are unary encoded to reduce glitches. The multiplying DAC consists of binary-weighted current sources switched by the partial products of the inputs. Test results show that the DAC has 12-bit accuracy after digital trimming, operates up to 600 MS/s and provides differential outputs of 0.5 V into 50 Omega loads. The SFDR is over 60 dBc below 20 MHz with a maximum of 72 dBc. Radiation tests show the nonlinear DAC can tolerate a total ionizing dose of 200 Krad Si.
  Circuits and Systems I: Regular Papers, IEEE Transactions on 11/2008; · 1.97 Impact Factor
• Conference Proceeding: Static Frequency Divider with Enhanced Frequency Performance

  P. Upadhyaya, G.S. La Rue
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  ABSTRACT: This paper presents the design and measured results of a novel static frequency divider that operates at a frequency 28% higher than a current-mode logic (CML) divider. The frequency divider was designed and implemented in IBM's 0.5 mum SiGe BiCMOS technology with an f_T of 47 GHz. The divider adds an additional delayed clock phase to a conventional CML- based divider. Measured results show operation up to 26 GHz with power dissipation of 59 mW compared to a CML divider that operates up to 20.4 GHz with power dissipation of 54.6 mW.
  Microelectronics and Electron Devices, 2008. WMED 2008. IEEE Workshop on; 05/2008
• Article: A Novel SiGe PIN Diode SPST Switch for Broadband T/R Module

  Pinping Sun, P. Upadhyaya, Dong-Ho Jeong, D. Heo, G.S. La Rue
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  ABSTRACT: A novel octagonal SiGe p-type intrinsic n-type (PIN) diode single pole single throw (SPST) switch is first implemented in a standard 0.18-mum SiGe BiCMOS technology. Distinctive radio frequency performance of monolithic silicon PIN diode switch is achieved for broadband applications with improvement of its geometry. Over the 2-16GHz frequency band, the PIN diode SPST switch exhibits an insertion loss of less than 1dB and isolation between 42dB to 19dB. An accurate small signal model of series PIN diode is also presented
  IEEE Microwave and Wireless Components Letters 06/2007; · 1.72 Impact Factor
• Source

  Available from: lw23.com

  Article: Fast acquisition clock and data recovery circuit with low jitter

  Ruiyuan Zhang, G.S. La Rue
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  ABSTRACT: This paper presents a half-rate clock and data recovery circuit (CDR)that combines the fast acquisition of a phase selection (PS) delay-locked loop (DLL) with the low jitter of a phase-locked loop (PLL). The PLL acquisition time improves considerably with use of a phase frequency magnitude detector(PFMD) that feeds back an estimate of the magnitude of the frequency difference in addition to the sign. Measurements in 0.5μm CMOS technology show operation up to 700 Mb/s, a 7% acquisition range, an initial acquisition time of 8 bit times with jitter of 30% bit time, and jitter of 16 ps after the PLL acquires lock. With a phase frequency detector (PFD), the PLL locks in about 700 ns from an initial frequency difference of 7%. Measurements using a PFMD show the 700 ns PLL acquisition time is reduced on average by about a factor of 5 to 140 ns from an initial 7% frequency difference. The power dissipation is 300mW.
  IEEE Journal of Solid-State Circuits 06/2006; · 3.23 Impact Factor
• Article: Accurate SPICE models for CMOS analog radiation-hardness-by-design

  C.L. Champion, G.S. La Rue
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  ABSTRACT: A new accurate modeling technique based on conformal mapping provides SPICE models for edgeless field-effect transistors (FETs) with arbitrary gate geometries for analog radiation-hardness-by-design. Generated models are compared to data measured from FETs with annular and other geometries fabricated on TSMC 0.25 μm and 0.18 μm processes. Currents, output resistances and capacitances all typically agree to within 10% of measured data. Application of the model to alternative gate geometries useful for analog radiation hardened design is explored.
  IEEE Transactions on Nuclear Science 01/2006; · 1.45 Impact Factor
• Conference Proceeding: Parallel phase accumulator architecture for DDFS

  I. Horowitz, G.S. La Rue
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  ABSTRACT: A parallel architecture is described for a phase accumulator (PA) in a direct digital frequency synthesizer (DDFS) intended for space-based applications. A comparison is made between the parallel and pipelined PA architectures in a 0.18 mum CMOS technology. The parallel architecture dissipates about 1/3 less power while achieving performance at least as high as the pipelined architecture. The accumulator designs are hardened against latch-up, total dose effects and single-event upsets through the use of guard rings, FET gate geometry and triple-mode redundancy (TMR) hardware
  Microelectronics and Electron Devices, 2005. WMED '05. 2005 IEEE Workshop on; 05/2005
• Conference Proceeding: Design of a radiation-hard DDFS

  Zhihe Zhou, I. Horowitz, G.S. La Rue
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  ABSTRACT: A radiation hardened direct digital frequency synthesizer (DDFS) was designed in 0.18 mum CMOS technology. A novel 14-bit nonlinear DAC is used to generate sine waves using a piecewise quadratic approximation. The nonlinear DAC effectively reduces lookup table size and total power dissipation. The DDFS is reconfigurable, has built-in automatic calibration and provides quadrature differential outputs. The 32-bit parallel phase accumulator provides 0.5 Hz frequency resolution and incorporates single-event upset (SEU) detection and correction circuitry. Digital and analog circuits are designed using radiation hard by design (RHBD) techniques. Simulation results show that 80 dB SFDR can be achieved for frequencies below 250 MHz at 2 GSps
  Microelectronics and Electron Devices, 2005. WMED '05. 2005 IEEE Workshop on; 05/2005
• Source

  Available from: wsu.edu

  Conference Proceeding: A low-power 16-bit 500 kS/s ADC

  Haidong Guo, D.M. Rector, G.S. la Rue
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  ABSTRACT: A 6.2 mW 16-bit 500 kSps charge redistribution self calibrating successive approximation analog-to-digital converter (ADC) is described. It has an input range of 2 V, a resolution of 16 bits and operates with +/- 1.5 V supplies. Simulations show a signal-to-noise ratio of 95 dB for an effective accuracy of 15 bits in 0.25 mum CMOS technology. A novel interleaving architecture and an improved comparator design contribute to reducing the power while maintaining the accuracy and speed. The ADC is intended to digitize the amplified neurophysiological signals from a companion 16-channel sensor IC
  Microelectronics and Electron Devices, 2005. WMED '05. 2005 IEEE Workshop on; 05/2005
• Conference Proceeding: Clock and data recovery circuits with fast acquisition and low jitter

  Ruiyuan Zhang, G.S. La Rue
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  ABSTRACT: This paper presents a half-rate clock and data recovery circuit (CDR) that combines the best features, fast acquisition and low jitter, of digital phase selection and phase-lock-loop (PLL) CDR circuits. This CDR circuit consists of a phase selector, which can lock to the data in just a few clock cycles but has high jitter, and a PLL, which requires a much longer lock time but provides a low-jitter clock after locking. Fabricated in a 0.5 μm CMOS process, the combined CDR achieves operation up to 750 Mbps. Measurements show at least a 6% acquisition range, an initial acquisition time of 8 bit times with jitter of 30% bit time, and jitter of 16 ps at 688 Mbps after a PLL lock time of 700 ns. Power dissipation is 300 mW and die area is 1.4 × 1.4 mm².
  Microelectronics and Electron Devices, 2004 IEEE Workshop on; 02/2004
• Conference Proceeding: Non-linear DAC implementations in DDFS

  Zhihe Zhou, I. Horowitz, G.S. La Rue
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  ABSTRACT: A technique to reduce ROM size and therefore power dissipation in direct digital frequency synthesizers (DDFS) is to use a non-linear DAC to approximate the sine function. Piecewise-linear and piecewise-quadratic approximations were investigated for a 12, 14 and 16-bit non-linear DAC in terms of the required ROM size, achievable spurious-free dynamic range (SFDR) and implementation complexity. Results show that 94 dB SFDR can be achieved using a 16-segment quadratic approximation, DAC resolution of 14-bits and a 5-bit squaring circuit. The required ROM size is only 256 bits.
  Microelectronics and Electron Devices, 2004 IEEE Workshop on; 02/2004
• Source

  Available from: wsu.edu

  Conference Proceeding: A low-power low-noise sensor IC

  Haidong Guo, C.L. Champion, D.M. Rector, G.S. La Rue
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  ABSTRACT: An IC for acquisition of 16 electrophysiology signals in mice is described. Each channel includes programmable gains from 10 to 1000, a 7 kHz low-pass 4th-order Butterworth filter and a sample and hold. Simulations predict 14-bit accuracy up to 7 kHz. The integrated noise from 1 Hz to 7 kHz is 1.9 μV/Hz¹2 /. The +/-0.3V dc input offset of each channel is cancelled with 7-bit DACs controlling the bulk of the first opamp input transistors and 6-bit DACs on the 2^nd stage. Total power dissipation is 13.5 mW using a 3V supply. Die area is 6 mm² in a 0.25 μ process.
  Microelectronics and Electron Devices, 2004 IEEE Workshop on; 02/2004
• Source

  Available from: wsu.edu

  Conference Proceeding: 40 Gbps SiGe pattern generator IC with variable clock skew and output levels

  M.J. Zahller, G.S. La Rue
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  ABSTRACT: A single-chip 40 Gbps pattern generator design in 0.18 mum SiGe BiCMOS technology is described. An on-chip 128times128 bit RAM with an access time of 3 ns stores the data pattern. A hybrid 128:1 CMOS/ECL multiplexer increases the output data rate from the RAM to 40 Gbps. The output driver is back terminated with 50 ohms and provides programmable levels in the range -2 V to 2 V into a 50 ohm load. The pattern dependent jitter is under 1 ps at all output levels. The clock can be delayed by a programmable number of clock cycles plus a vernier delay of up to 50 ps in 0.2 ps steps. Power dissipation is up to 550 mW depending on the output amplitude and termination voltage
  Microelectronics and Electron Devices, 2006. WMED '06. 2006 IEEE Workshop on;