D. Okada

University of Central Florida, Orlando, FL, United States

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Publications (6)5.73 Total impact

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    ABSTRACT: This paper investigates the poor body diode reverse recovery characteristics of lateral power MOSFETs. It is found that the lightly doped P-substrate accommodates an excessive amount of minority carrier storage charge when the body diode between the P-substrate and N-drain is forward biased. The excessive storage charge causes a long tail in the reverse recovery current waveform of the body diode. Two LDMOS structural variations are explored to improve the body diode performance for hard-switching synchronous rectifier DC/DC converter applications. Both simulation and experimental results show that over 90% reduction in reverse recovery charge can be achieved with the new device structures.
    Power Semiconductor Devices and IC's, 2008. ISPSD '08. 20th International Symposium on; 06/2008
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    ABSTRACT: This paper presents a comparative study of lateral and trench power MOSFETs in hard switching synchronous buck converters operating in the multi-MHz frequency range based on a mixed-mode device/circuit modeling approach. Detailed power loss analysis is performed for the control and synchronous MOSFETs. It is observed that the inherently low gate charge QG of lateral MOSFETs offers significant reduction in gate drive losses, which become increasingly important in the multi-MHz frequency range and especially light load conditions. Furthermore, the power loss due to the reverse recovery of the SyncFET body diode becomes a major limiting factor in the MHz frequency range for both trench and lateral MOSFETs. This factor will eventually determine the maximum practical switching frequency of the buck converter.
    Power Electronics Specialists Conference, 2007. PESC 2007. IEEE; 07/2007
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    ABSTRACT: DC/DC converters to power future CPU cores mandate low-voltage power metal-oxide semiconductor field-effect transistors (MOSFETs) with ultra low on-resistance and gate charge. Conventional vertical trench MOSFETs cannot meet the challenge. In this paper, we introduce an alternative device solution, the large-area lateral power MOSFET with a unique metal interconnect scheme and a chip-scale package. We have designed and fabricated a family of lateral power MOSFETs including a sub-10 V class power MOSFET with a record-low R<sub>DS(ON)</sub> of 1mΩ at a gate voltage of 6V, approximately 50% of the lowest R<sub>DS(ON)</sub> previously reported. The new device has a total gate charge Q<sub>g</sub> of 22nC at 4.5V and a performance figures of merit of less than 30mΩ-nC, a 3× improvement over the state of the art trench MOSFETs. This new MOSFET was used in a 100-W dc/dc converter as the synchronous rectifiers to achieve a 3.5-MHz pulse-width modulation switching frequency, 97%-99% efficiency, and a power density of 970W/in<sup>3</sup>. The new lateral MOSEFT technology offers a viable solution for the next-generation, multimegahertz, high-density dc/dc converters for future CPU cores and many other high-performance power management applications.
    IEEE Transactions on Power Electronics 02/2006; · 5.73 Impact Factor
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    ABSTRACT: P-channel power MOSFETs are widely used in portable electronics products as the load switch. We report a new 12 V P-channel chip-scale lateral power MOSFET with ultra-low on-resistance and small package footprint. The product of RDS (ON) and footprint area of the lateral MOSFET is reduced by nearly 50% comparing to the conventional trench MOSFET with the same voltage rating. We have developed an innovative metal interconnect and chip-scale packaging approach to overcome the "scaling issue" which limits the chip size and current rating of traditional lateral power devices. The lateral MOSFET is designed and fabricated based on a standard 0.5 μm CMOS process, and packaged in flip-chip forms using a wafer bumping technology. P-channel Lateral Power<sup>™</sup> MOSFETs provide a good solution for load switching in all sorts of battery-powered portable electronics products.
    Applied Power Electronics Conference and Exposition, 2005. APEC 2005. Twentieth Annual IEEE; 04/2005
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    ABSTRACT: The conduction performance of low-voltage lateral power semiconductor devices deteriorates considerably with increasing device size due to the parasitic resistance of metal interconnects, commonly known as the "scaling limitation". In this paper, we introduce an innovative concept to overcome the problem by integrating a unique metal interconnect scheme with chip-scale packaging. We have designed and fabricated a sub-10 V class power MOSFET with a record-low R<sub>DSON</sub> of 1 mΩ at a gate voltage of 6 V, or 1.25 mΩ at a gate voltage of 4.5 V, approximately 50% of the lowest R<sub>DSON</sub> previously reported. The new device has a total gate charge Q<sub>g</sub> of 22 nC at 4.5 V and a performance figure of merit of less than 30 mΩ-nC. This represents a 3× improvement over the state of the art trench MOSFETs. The new MOSEFT technology can be used to enable next-generation, multi-MHz, high-density DC/DC converters for future CPU cores and many other high-performance power management applications.
    Power Semiconductor Devices and ICs, 2004. Proceedings. ISPSD '04. The 16th International Symposium on; 06/2004
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    ABSTRACT: DC/DC converters to power future CPU or DSP cores mandate low-voltage power MOSFETs with ultra low on-resistance and gate charge. Conventional trench MOSFETs cannot meet the challenge. We introduce an alternative device technology, the discrete lateral power MOSFETs, to overcome the limitations associated with the vertical trench or planar MOSFETs. We report a family of 7V, 20V, and 30V lateral discrete power MOSFETs with figures of merit 2-3 times better than the state-of-the-art trench MOSFETs. We have developed an innovative metal interconnect and chip-scale packaging approach to overcome the "scaling barrier" which limits the chip size and current rating of the traditional lateral power devices. The lateral MOSFETs were designed and fabricated with a simplified CMOS process, and packaged in flip-chip forms using a wafer bumping technology. Lateral discrete power MOSFETs will become a viable enabling technology for next-generation, MHz-frequency, high-density DC/DC converters.
    Applied Power Electronics Conference and Exposition, 2004. APEC '04. Nineteenth Annual IEEE; 02/2004