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ABSTRACT: Considering gate-oxide reliability, a new electrostatic discharge (ESD) protection scheme with an on-chip ESD bus (ESD_BUS) and a high-voltage-tolerant ESD clamp circuit for 1.2/2.5 V mixed-voltage I/O interfaces is proposed. The devices used in the high-voltage-tolerant ESD clamp circuit are all 1.2 V low-voltage N- and P-type MOS devices that can be safely operated under the 2.5-V bias conditions without suffering from the gate-oxide reliability issue. The four-mode (positive-to-V<sub>SS</sub>, negative-to-V<sub>SS</sub>, positive-to-V<sub>DD,</sub> and negative-to-V<sub>DD</sub>) ESD stresses on the mixed-voltage I/O pad and pin-to-pin ESD stresses can be effectively discharged by the proposed ESD protection scheme. The experimental results verified in a 0.13-mum CMOS process have confirmed that the proposed new ESD protection scheme has high human-body model (HBM) and machine-model (MM) ESD robustness with a fast turn-on speed. The proposed new ESD protection scheme, which is designed with only low- voltage devices, is an excellent and cost-efficient solution to protect mixed-voltage I/O interfaces.
IEEE Transactions on Electron Devices 07/2008; · 2.32 Impact Factor
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ABSTRACT: A new electrostatic discharge (ESD) protection structure of high-voltage p-type silicon-controlled rectifier (HVPSCR) that is embedded into a high-voltage p-channel MOS (HVPMOS) device is proposed to greatly improve the ESD robustness of the vacuum-fluorescent-display (VFD) driver IC for automotive electronics applications. By only adding the additional n+ diffusion into the drain region of HVPMOS, the transmission-line-pulsing-measured secondary breakdown current of the output driver has been greatly improved to be greater than 6 A in a 0.5- mum high-voltage complementary MOS process. Such ESD-enhanced VFD driver IC, which can sustain human-body-model ESD stress of up to 8 kV, has been in mass production for automotive applications in cars without the latchup problem. Moreover, with device widths of 500, 600, and 800 mum, the machine-model ESD levels of the HVPSCR are as high as 1100,1300, and 1900 V, respectively.
IEEE Transactions on Device and Materials Reliability 10/2007; · 1.54 Impact Factor
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ABSTRACT: The ESD robustness on different device structures and layout parameters of high-voltage (HV) NMOS has been investigated in 40-V CMOS process with silicon verification. It was demonstrated that a specific structure of HV n-type silicon controlled rectifier (HVNSCR) embedded into HV NMOS without N-drift implant in the drain region has the best ESD robustness. Moreover, due to the different current distributions in HV NMOS and HVNSCR, the trends of the TLP-measured It2 under different spacings from the drain diffusion to polygate are different.
Physical and Failure Analysis of Integrated Circuits, 2007. IPFA 2007. 14th International Symposium on the; 08/2007
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ABSTRACT: The dependences of drift implant and layout parameters on electrostatic discharge (ESD) robustness in a 40-V CMOS process have been investigated in silicon chips. From the experimental results, the high-voltage (HV) MOSFETs without drift implant in the drain region have better transmission line pulsing (TLP)-measured secondary breakdown current (It2) and ESD robustness than those with drift implant in the drain region. Furthermore, the It2 and ESD level of HV MOSFETs can be increased as the layout spacing from the drain diffusion to polygate is increased. It was also demonstrated that a specific test structure of HV n-type silicon-controlled rectifier (HVNSCR) embedded into HV NMOS without N-drift implant in the drain region has the excellent TLP-measured It2 and ESD robustness. Moreover, due to the different current distributions in HV NMOS and HVNSCR, the dependences of the TLP-measured It2 and human-body-model ESD levels on the spacing from the drain diffusion to polygate are different.
IEEE Transactions on Device and Materials Reliability 07/2007; · 1.54 Impact Factor
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ABSTRACT: The dependences of device structures and layout parameters on ESD robustness in a 40-V CMOS process have been investigated in silicon chips. From the experimental results, the high-voltage (HV) MOSFETs without drift implant in the drain region have better TLP-measured It2 and ESD robustness than those with drift implant in the drain region. Furthermore, the It2 and ESD level of HV MOSFETs can be increased as the layout spacing from the drain diffusion to polygate is increased
Integrated Reliability Workshop Final Report, 2006 IEEE International; 10/2006
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ABSTRACT: An ESD protection design for 1.2V/2.5V mixed-voltage I/O interfaces is discussed. A high-voltage-tolerant power-rail ESD clamp circuit is used; it is realized with low-voltage devices in a 0.13mum CMOS process. The four-mode ESD stresses on the mixed-voltage I/O pad and the whole-chip pin-to-pin ESD protection can be discharged by the proposed ESD protection scheme
Solid-State Circuits Conference, 2006. ISSCC 2006. Digest of Technical Papers. IEEE International; 03/2006
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ABSTRACT: Electrostatic discharge (ESD) protection design for mixed-voltage I/O interfaces with the low-voltage-triggered p-n-p (LVTp-n-p) device in CMOS technology is proposed. The LVTp-n-p, by inserting N+ or P+ diffusion across the junction between N-well and P-substrate of the p-n-p device, is designed to protect the mixed-voltage I/O interfaces for signals with voltage levels higher than VDD (over-VDD) and lower than VSS (underVSS). The LVTp-n-p devices with different structures have been investigated and compared in CMOS processes. The experimental results in a 0.35-μm CMOS process have proven that the ESD level of the proposed LVTp-n-p is higher than that of the traditional p-n-p device. Furthermore, layout on LVTp-n-p device for ESD protection in mixed-voltage I/O interfaces is also optimized in this work. The experimental results verified in both 0.35- and 0.25-μm CMOS processes have proven that the ESD levels of the LVTp-n-p drawn in the multifinger layout style are higher than that drawn in the single-finger layout style. Moreover, one of the LVT p-n-p devices drawn with the multifinger layout style has been used to successfully protect the input stage of an asymmetric digital subscriber line (ADSL) IC in a 0.25-μm salicided CMOS process.
IEEE Transactions on Device and Materials Reliability 10/2005; · 1.54 Impact Factor
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ABSTRACT: Layout optimization on low-voltage-triggered PNP (LVTPNP) devices for ESD protection in mixed-voltage I/O interfaces is proposed in this paper. The experimental results in both 0.35-μm and 0.25-μm CMOS processes have proven that the ESD levels of the LVTPNP drawn in the multi-finger layout style are higher than that drawn in the original layout style. Moreover, the LVTPNP device in multi-finger layout style has been implemented in a 0.25-μm salicided CMOS process to protect successfully the input stage of an ADSL IC with power-rail ESD clamp circuit.
Physical and Failure Analysis of Integrated Circuits, 2004. IPFA 2004. Proceedings of the 11th International Symposium on the; 08/2004
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ABSTRACT: An ESD protection design for mixed-voltage I/O interfaces with low-voltage-triggered PNP (LVTPNP) devices is proposed in this paper. The LVTPNP, by inserting N+ or P+ diffusion across the junction between the N-well and P-substrate of the PNP devices, is designed to protect the mixed-voltage I/O pads for signals with voltage levels higher than VDD (over-VDD) and lower than VSS (under-VSS). The experimental results in a 0.35 μm CMOS process have proven that the ESD level of the proposed LVTPNP is higher than that of the traditional PNP device.
Quality Electronic Design, 2004. Proceedings. 5th International Symposium on; 02/2004
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ABSTRACT: Electrostatic discharge (ESD) protection design for mixed-voltage I/O interfaces has been one of the key challenges of system-on-a-chip (SOC) implementation in nanoscale CMOS processes. The on-chip ESD protection circuit for mixed-voltage I/O interfaces should meet the gate-oxide reliability constraints and prevent the undesired leakage current paths. This paper presents an overview on the design concept and circuit implementations of ESD protection designs for mixed-voltage I/O interfaces with only low-voltage thin-oxide CMOS transistors. Especially, the ESD protection designs for mixed-voltage I/O interfaces with ESD bus and high-voltage-tolerant power-rail ESD clamp circuits are presented and discussed.
Microelectronics Reliability.
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ABSTRACT: An ESD protection structure of HVPSCR embedded into the high-voltage PMOS device is proposed to greatly improve ESD robustness of the vacuum-fluorescent-display (VFD) driver IC for automotive electronics applications. By only adding the additional N+ diffusion into the drain region of HVPMOS, the It2 of output cell has been greatly improved form 0.07A to be greater than 6A within the almost same layout area. Such an ESD-enhanced VFD driver IC has been in mass production for automotive applications in car to sustain HBM ESD stress of up to 8kV.
Physical and Failure Analysis of Integrated Circuits, 2005. IPFA 2005. Proceedings of the 12th International Symposium on the;
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ABSTRACT: The dependence of device structures and layout parameters on ESD robustness of HV MOSFETs in high-voltage 40-V CMOS process has been investigated by device simulation and verified in silicon test chips. It was demonstrated that a new ESD protection structure with p-type SCR embedded into the HV PMOS has the highest ESD robustness in a given 40-V CMOS process.
Reliability Physics Symposium, 2008. IRPS 2008. IEEE International;
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ABSTRACT: With consideration on the gate-oxide reliability, the new ESD protection design with ESD bus for 1.2/2.5-V mixed-voltage I/O interfaces is reported by using the new proposed high-voltage-tolerant power-rail electrostatic discharge (ESD) clamp circuit. This proposed power-rail ESD clamp circuit with only 1.2-V low-voltage NMOS/PMOS devices can be operated under the 2.5-V input conditions without suffering the gate-oxide reliability issue. The experimental results in a 0.13-mum CMOS process have confirmed that the proposed power-rail ESD clamp circuit has high human-body-model (HBM) and machine-model (MM) ESD robustness and fast turn-on speed. The proposed power-rail ESD clamp circuit is an excellent ESD protection solution to the mixed-voltage I/O interfaces
Research in Microelectronics and Electronics 2006, Ph. D.;
