F. Farbiz

University of Tehran, Tehrān, Ostan-e Tehran, Iran

Are you F. Farbiz?

Claim your profile

Publications (18)7.71 Total impact

  • Conference Proceeding: An adaptive nonlinear estimator for the MEMS capacitive accelerometer based on adaptive input-output feedback linearization
    [show abstract] [hide abstract]
    ABSTRACT: This paper presents a new estimator for the conventional capacitive MEMS accelerometer. This scheme is realized by adding an adaptive nonlinear observer to a conventional PID closed loop system. This estimator is used for online estimation of the parameter variations for MEMS accelerometers and gives the capability of self testing to the system. We outline the design of an online estimator for a capacitive MEMS accelerometer to detect changes in spring stiffness (k) and damping factor (b).
    Semiconductor Device Research Symposium, 2007 International; 01/2008
  • Conference Proceeding: A novel SiGe-On-Insulator IMOS device with reduced bias voltages
    [show abstract] [hide abstract]
    ABSTRACT: In this paper we have investigated the possibility of implanting SiGe-on-insulator technology to reduce the breakdown voltage in an p-IMOS device. Of course the concept can be extended to n-IMOS devices as well. The structure of the proposed SGOI-IMOS is shown and the parameters employed in simulation are listed in table 1.
    Semiconductor Device Research Symposium, 2007 International; 01/2008
  • Conference Proceeding: A QR decomposition based mixture model algorithm for background modeling
    M. Amintoosi, F. Farbiz, M. Fathy
    [show abstract] [hide abstract]
    ABSTRACT: This paper presents a new algorithm for background modeling in a sequence of images, even if there are foreground objects in each frame. We develop a QR decomposition based algorithm to remove foreground pixels from the image and then we construct the background model using mixture of Gaussian algorithm, MoG. We split the image into small blocks and construct the background blocks using R-values taken from QR decomposition which indicate the degree of significance of the decomposed parts. The simulation results show the better performance of the proposed algorithm in compare with conventional methods on modeling static background images.
    Information, Communications & Signal Processing, 2007 6th International Conference on; 01/2008
  • Conference Proceeding: Using level restoring method for dual supply voltage
    K. Sadeghi, M. Emadi, F. Farbiz
    [show abstract] [hide abstract]
    ABSTRACT: A new level converter for use in dual voltage SOI digital circuits is presented. This technique uses the idea of keeper transistors, and consumes less power compared to the traditional methods. The effects of load capacitance on the circuit are studied by extensive simulations.
    VLSI Design, 2006. Held jointly with 5th International Conference on Embedded Systems and Design., 19th International Conference on; 02/2006
  • Conference Proceeding: Investigation of Gate Tunnelling Leakage Current in a Novel Fully Depleted SOI MOSFET with a Thin Oxide
    [show abstract] [hide abstract]
    ABSTRACT: Not Available
    Semiconductor Device Research Symposium, 2005 International; 02/2005
  • Source
    Conference Proceeding: Voltage and sizing optimization for low power buffered digital designs
    [show abstract] [hide abstract]
    ABSTRACT: A circuit design style with separate logic and buffer stages is investigated for its energy and delay characteristics. Then a new numerical approach is proposed for determining the optimum transistor sizing and supply voltage according to the minimum energy-delay product as a figure of merit (FOM). The results agree perfectly with the simulation data gathered from the SPICE simulation and are much more accurate than the ones proposed in the previous works.
    Microelectronics, 2004. ICM 2004 Proceedings. The 16th International Conference on; 01/2005
  • Conference Proceeding: An analytical approach to hardware-friendly adaptive learning rate neural networks
    [show abstract] [hide abstract]
    ABSTRACT: In this paper hardware implementation of adaptive learning rate neural networks is studied. Some design guidelines are presented to improve integration of learning algorithm into the hardware. By using them, it is possible to design high performance neural networks, which are capable of handling a rapidly-conversing learning algorithm in analog chips. The analytical approach developed in this work provides more insight towards tuning of a reliable design. Our experimental results prove that this approach performs above the conventional fixed learning rate approach, and is almost comparable to the ideal gradient based adaptive approach.
    Microelectronics, 2004. ICM 2004 Proceedings. The 16th International Conference on; 01/2005
  • Source
    Conference Proceeding: Efficient rate adjustment hardware for on-chip learning
    [show abstract] [hide abstract]
    ABSTRACT: This paper presents a new approach to facilitate the implementation of adaptive adjustment of on-chip rate learning in feed forward neural networks. A typical multi layer perceptron (MLP) network with controlled learning method is assumed as the target of the design and a Gilbert amplifier cell is used to tune an adaptive learning rate to find an optimum trajectory for robust design.
    Devices, Circuits and Systems, 2004. Proceedings of the Fifth IEEE International Caracas Conference on; 12/2004
  • Conference Proceeding: Gain boosted amplifier design for low power-high speed applications
    [show abstract] [hide abstract]
    ABSTRACT: In this paper, different models of gain enhanced amplifier are compared and the most accurate one is chosen. Based on this model, complete symbolic small signal analysis is performed and a design procedure leading to high-speed gain boosted amplifier is presented. Modeling of the GBTA is discussed. The optimization procedure and the formulation of the settling time are also derived.
    Circuits and Systems, 2004. NEWCAS 2004. The 2nd Annual IEEE Northeast Workshop on; 07/2004
  • Conference Proceeding: Design guidelines for leakage control transistor
    F. Farbiz, M. Emadi, B. Foruzandeh
    [show abstract] [hide abstract]
    ABSTRACT: This paper investigates the effects of transistor sizing of the sleep transistor on the power consumption and speed. A method is proposed to handle the power-delay trade off and a new transistor arrangement is proposed. Simulations show how much is the appropriate size of sleep transistor with respect to the gate size. This paper deals with the effective combination of stack transistor insertion method and the input vector control technique. Sizing considerations for both the proposed and conventional methods are examined.
    Circuits and Systems, 2004. NEWCAS 2004. The 2nd Annual IEEE Northeast Workshop on; 07/2004
  • Conference Proceeding: Sizing consideration for leakage control transistor
    [show abstract] [hide abstract]
    ABSTRACT: In this paper, we report the use of the Genetic Algorithm (GA) to determine the optimum size of the leakage control transistor for low power applications. In the optimization, the energy-delay product is minimized. The transistor is modeled by a neural network to increase the speed and the accuracy of the calculations.
    VLSI Design, 2004. Proceedings. 17th International Conference on; 02/2004
  • Conference Proceeding: Power and delay estimation of CMOS inverters using fully analytical approach
    [show abstract] [hide abstract]
    ABSTRACT: In this paper, a new simple yet accurate model for determining delay and power consumption of static CMOS inverters is introduced. This analytical model uses the modified version of n-th power law MOSFET model which is appropriate for short channel devices. The short-circuit current, which is used in the calculation of the power consumption, is modeled by a piecewise linear interpolation scheme. For evaluation the delay of the inverter, an accurate model is presented. Although the proposed model is much simpler compared to the previously reported ones, it has a very good accuracy which is confirmed with HSPICE simulations.
    Mixed-Signal Design, 2003. Southwest Symposium on; 03/2003
  • Article: A new fuzzy logic filter for image enhancement.
    [show abstract] [hide abstract]
    ABSTRACT: This paper presents a new fuzzy-logic-control based filter with the ability to remove impulsive noise and smooth Gaussian noise, while, simultaneously, preserving edges and image details efficiently. To achieve these three image enhancement goals, we first develop filters that have excellent edge-preserving capability but do not perform well in smoothing Gaussian noise. Next, we modify the filters so that they perform all three image enhancement tasks. These filters are based on the idea that individual pixels should not be uniformly fired by each of the fuzzy rules. To demonstrate the capability of our filtering approach, it was tested on several different image enhancement problems. These experimental results demonstrate the speed, filtering quality, and image sharpening ability of the new filter.
    IEEE Transactions on Systems Man and Cybernetics Part B (Cybernetics) 02/2000; 30(1):110-9. · 3.08 Impact Factor
  • Conference Proceeding: An extended iterative method for image enhancement based on fuzzy logic
    F. Farbiz, M.B. Menhaj
    [show abstract] [hide abstract]
    ABSTRACT: The paper presents an extension of our previous fuzzy logic based filtering approach whose high performance in mixed noise environments has been reported by F. Furbiz et al. (1998). This filter has also kept the general property of not letting each pixel be uniformly fired by each of the fuzzy rules. It further aims at compressing the membership functions of fuzzy linguistic terms in each iteration to enhance the filtering ability. We show through some experiments how powerful our filter is in image enhancement
    Knowledge-Based Intelligent Information Engineering Systems, 1999. Third International Conference; 01/2000
  • Conference Proceeding: A modified iterative fuzzy control based filter for image enhancement with multiplicative noise removal property
    F. Farbiz, M.B. Menhaj
    [show abstract] [hide abstract]
    ABSTRACT: In this paper we propose a modified iterative fuzzy logic control based filter acronymed by MIFCF for removing impulsive noise, smoothing additive & multiplicative Gaussian noise with preserving image edges and details. The high performance of our method especially in removing the multiplicative noise, in compared with those of recently proposed filters, is demonstrated by some experiments
    Image Processing, 1999. ICIP 99. Proceedings. 1999 International Conference on; 02/1999
  • Conference Proceeding: Fixed point filter design for image enhancement using fuzzy logic
    [show abstract] [hide abstract]
    ABSTRACT: This paper presents a new fuzzy-logic-control based filter with the properties of removing impulsive noise and smoothing out Gaussian noise while, simultaneously, preserving edges and image details efficiently. To reach the above three goals of the image enhancement problem, we employ the concepts of fuzzy logic control to design a filter to perform all the three tasks mentioned above. This filter is mainly based on the idea that each pixel is not allowed to be uniformly fired by each of the fuzzy rules. To demonstrate how good our filtering approach works, several different cases of image enhancement problem have been considered. From the experimental results we may list the concluding remark of the proposed filtering approach: (i) no need of floating point calculations, (ii) very fast performance of the filter compared with other proposed filters, (iii) introducing a measure to demonstrate quantitatively the quality behaviour of the filters in edge preserving, (iv) high quality of filtering especially for complex images
    Image Processing, 1998. ICIP 98. Proceedings. 1998 International Conference on; 11/1998
  • Source
    Conference Proceeding: An iterative method for image enhancement based on fuzzy logic
    [show abstract] [hide abstract]
    ABSTRACT: This paper presents a new filtering approach based on fuzzy-logic which has high performance in mixed noise environments. This filter is mainly based on the idea that each pixel is not allowed to be uniformly fired by each of the fuzzy rules. We perform several test experiments in order to highlight the merit of the proposed method. The results are very promising and indicating the high performance of the proposed filter in image restoration compared with those of the filters which have been previously cited in image processing literature
    Acoustics, Speech and Signal Processing, 1998. Proceedings of the 1998 IEEE International Conference on; 06/1998 · 4.63 Impact Factor
  • Source
    Article: A Background Model Initialization Algorithm Based on QR-Decomposition
    [show abstract] [hide abstract]
    ABSTRACT: Background subtraction is a major part of many motion detection, tracking and surveillance systems. In this paper a new algorithm for the purpose of the background model initialization has been presented. The key idea of the proposed method lies in the identification of the background based on QR-Decomposition method in linear algebra. R-values produced with QR-Decomposition can be applied to decompose a given system to indicate the degree of the significance of the decomposed parts. We split the image into small blocks and select the background blocks with the weakest contribution, according to the assigned R-values. The main advantage of the proposed method is that in contrast to many other methods, here, there is no need for an empty scene with no foreground object. Simulation results showed that the proposed method produced better background model with respect to some others.

Institutions

  • 2004–2008
    • University of Tehran
      • School of Electrical and Computer Engineering
      Tehrān, Ostan-e Tehran, Iran
  • 2006
    • Sharif University of Technology
      Tehrān, Ostan-e Tehran, Iran
  • 1998–2000
    • Amirkabir University of Technology
      • Department of Electrical Engineering
      Tehrān, Ostan-e Tehran, Iran