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S. Minehane,
J. Cheng,
T. Nakatani,
S. Moriyama,
B. Aghdaie, M. Sengupta,
S. Saxena,
S. Winters,
H. Karbasi,
M. Quarantelli,
S. Tonello,
M. Redford
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ABSTRACT: The inclusion of circuit-level blocks, such as ring oscillators, operational amplifiers and A/D or D/A converters, in technology characterization test chips is now a well-established practice. Such figure-of-merit (FoM) circuit blocks provide a means of judging technology performance and variability on-wafer during the technology development phase. In addition, FoM blocks are used to validate the ability of a PDK in capturing process behavior. This paper describes an extension of this concept to the RF domain, for a high-performance 0.18mum SiGe:C-BiCMOS technology. The design of six different RF-FoM blocks, typically found in a transceiver, is presented. Test structure design considerations, including layout, pad-frame choice and probe-card design, are described. Finally, measured statistical results are presented. These designs enabled PDK verification and high-volume yield product samples.
Microelectronic Test Structures, 2007. ICMTS '07. IEEE International Conference on; 04/2007
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ABSTRACT: Integrated circuits (ICs) must be robust to manufacturing variations. Circuit simulation at a set of worst case corners is a computationally efficient method for verifying the robustness of a design. This paper presents a new statistical methodology to determine the worst case corners for a set of circuit performances. The proposed methodology first estimates response surfaces for circuit performances as quadratic functions of the process parameters with known statistical distributions. These response surfaces are then used to extract the worst case corners in the process parameter space as the points where the circuit performances are at their minimum/maximum values corresponding to a specified tolerance level. Corners in the process parameter space close to each other are clustered to reduce their number, which reduces the number of simulations required for design verification. The novel concept of a relaxation coefficient to ensure that the corners capture the minimum/maximum values of all the circuit performances at the desired tolerance level is also introduced. The corners are realistic since they are derived from the multivariate statistical distribution of the process parameters at the desired tolerance level. The methodology is demonstrated with examples showing extraction of corners from digital standard cells and also the corners for analog/radio frequency (RF) blocks found in typical communication ICs.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 10/2005; · 1.27 Impact Factor
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ABSTRACT: The performance and variability of transistors with nanometer-scale feature sizes is sensitive to their layout style and environment. This paper describes the use of an enhanced MOS array test structure to provide accurate and precise estimates of the impact of layout on transistor characteristics for an advanced 130nm CMOS technology. Enhanced MOS arrays, combined with statistical analysis of the measurements, provide reliable information on the impact of layout on the transistor characteristics. This can then form the basis for technology development, design rule development and modeling.
Microelectronic Test Structures, 2004. Proceedings. ICMTS '04. The International Conference on; 04/2004
