A. Vladimirescu

Lodz University of Technology, Łódź, Łódź Voivodeship, Poland

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Publications (34)10.04 Total impact

  • Costin Anghel, Andrei Vladimirescu
    Solid-State Electronics. 01/2014; 97:1.
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    ABSTRACT: This work presents a Non-Volatile SRAM (NV-SRAM) cell, resilient to information loss. The cell features fast storage (20 ns) for the operating voltage of 1.0 V. The information is backed-up during POWER-DOWN/RESTORE cycle in two bipolar Oxide Resistive RAMs (OxRRAMs). The proposed NV-SRAM is designed with an 8T2R structure using 22 nm FDSOI technology and resistive memory devices based on HfO2. The stability and the reliability of the NV-SRAM cell is investigated by taking into account the variability of the transistors. It is shown that high ROFF/RON is necessary to ensure reliable RESTORE operation and high SRAM yield under cell area and power consumption constraints.
    Solid-State Electronics 12/2013; 90:99-106. · 1.48 Impact Factor
  • A. Makosiej, O. Thomas, A. Amara, A. Vladimirescu
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    ABSTRACT: This paper presents a predictive analysis of the high-density SRAM cell scaling from the stability and low power perspective. Based on a subthreshold SRAM analytical model [5] and a SRAM area-scaling model the Data Retention Voltage (DRV) defined as the lowest VDD that can be applied during standby without losing data, as well as the minimum supply voltage for reliable read and write (VMIN), are investigated. The analysis is performed for several future technology nodes down to the 18 nm node. It takes into account the impact of MOS key parameters: threshold voltage (VT), subthreshold slope, DIBL, body factor and Pelgrom's Coefficient AVT. It is demonstrated, that due to process variations, the use of bulk CMOS for sub-28 nm becomes very challenging and severely limits area and supply scaling. Thin-film technology such as Ultra-Thin Body and BOX (UTBB) FDSOI however, should allow stable and power- and area-efficient SRAM design scaling below the 22 nm node with DRV lower than 0.4 V.
    Circuits and Systems (ISCAS), 2013 IEEE International Symposium on; 01/2013
  • Hraziia, Andrei Vladimirescu, Amara Amara, Costin Anghel
    Solid-State Electronics 04/2012; · 1.48 Impact Factor
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    Adam Makosiej, Olivier Thomas, Andrei Vladimirescu, Amara Amara
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    ABSTRACT: This paper presents a methodology for the optimal design of CMOS 6T SRAM ultra-low-power (ULP) bitcells minimizing power consumption under strict stability constraints in all operating modes. An accurate analytical SRAM subthreshold model is developed for characterizing the cell behavior and optimizing its performance. The proposed design approach is demonstrated for an SRAM implemented in a 32nm CMOS UTBB-FDSOI technology. Stable operation in both read and write is obtained for the optimized cell at VDD=0.4V. Moreover, in the optimization process the standby and active power were reduced up to 10x and 3x, respectively.
    01/2012;
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    ABSTRACT: This paper describes the applicability of Tunnel FETs to commercial embedded Static Random-Access Memories (SRAM). Numerical device simulations were used first to optimize the performance of the TFET. The optimized TFETs show a steeper subthreshold slope than CMOS leading to a 5 orders of magnitude reduction in standby current. A look-up table model for circuit simulation of the TFET was developed based on characteristics obtained from TCAD simulations. A TFET SRAM cell is proposed and its stability is analyzed. Our novel 8T TFET SRAM cell operates at VDD=1V. The Read and Write Static Noise Margins are evaluated at 120mV and 200mV, with the operation speed of 300MHz and 1GHz in read and write respectively. The cell leakage is less than 10fA at VDD=1V. Our results show that TFETs are excellent candidates for embedded SRAMs due to their Ultra-Low Standby Power (LSTP).
    Circuits and Systems (ISCAS), 2012 IEEE International Symposium on; 01/2012
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    ABSTRACT: Planar fully-depleted SOI technology is becoming mainstream within STMicroelectronics, targeting modern mobile and consumer multimedia markets. This technology combines high performance and low power consumption, complemented by an excellent responsiveness to power management design techniques. The fabrication process is comparatively simple and is a low-risk evolutionary step from conventional planar bulk CMOS. At 28nm, we find that planar FD more than matches the peak performance of “G”-type bulk technology, at the cost and complexity of a low-power type technology, with better power efficiency across use cases than any of the conventional bulk CMOS flavors. FD implementation of a representative design offers 1.6×–7× speedup compared to bulk across a range of supply voltages.
    01/2012;
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    C. Anghel, Hraziia, A. Gupta, A. Amara, A. Vladimirescu
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    ABSTRACT: This paper presents the optimization of double-gate silicon (Si) tunnel field-effect transistors (TFETs). It shows that, for the heterodielectric structure, the I<sub>ON</sub> current is boosted by correctly positioning the source with respect to the gate edge. The second booster used in this paper is the Si thickness that is tuned in order to maximize the I<sub>ON</sub> current. The effects that lead to the performance increase are explained on a physical basis. We also demonstrate that the ambipolar character of the TFET is completely inhibited by using only one spacer of 30-nm length to separate the drain and the gate.
    IEEE Transactions on Electron Devices 07/2011; · 2.06 Impact Factor
  • T. Chawla, S. Marchal, A. Amara, A. Vladimirescu
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    ABSTRACT: Global and Environmental variations together are responsible for differences in timing from one die to another for an ASIC design. The tried and tested method of corners and margins is still the dominant method in ASIC industry to assure the timing characteristics of a design. However, the increasing margins limit the scaling of maximum achievable frequency for a given die size, especially because of minimum pulse width violation. The importance of clock tree pulse-width variations due to global N-to-P mismatch is increasing with decreasing pulse width. To continue scaling the clock frequency, we may need to make application specific margins and corners. In this work, we have estimated the impact of pulse width variations on standard cells in a clock library using industrial models and spice simulations. We found that by unbalancing the first stage of a cell with respect to rise and fall edge in a multiple supply voltage design, we could halve the pulse width variations with minimal effect on delay and slew.
    Microelectronics (ICM), 2009 International Conference on; 01/2010
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    ABSTRACT: A low-cost and high-manufacturability Multi-VT Ultra-Thin BOX and Body (UT2B) FDSOI technology is proposed for high-performance and low-leakage digital circuits. This concept allows setting up low, standard and high threshold voltage (VT) devices without degrading the good channel electrostatic control and the low VT dispersion of the FDSOI technology. Device electrical characteristics, process flow and physical design are described and the performance of digital circuits is evaluated.
    International Symposium on Circuits and Systems (ISCAS 2010), May 30 - June 2, 2010, Paris, France; 01/2010
  • A. Makosiej, A. Vladimirescu, O. Thomas, A. Amara
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    ABSTRACT: This paper presents a universal optimization model for Static Noise Margin (SNM) of Ultra Low Power (ULP) CMOS SRAMs in the presence of statistical variations. Distributions of retention and read SNM derived analytically, are analyzed as a function of the threshold voltages of the N and PMOS devices. The proposed model implemented in Matlab is applied to optimize yield by maximizing the μ/6σ of SNM in the presence of local statistical VT variation of 3σ.
    01/2010;
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    ABSTRACT: An improved double-gate tunnel field-effect transistor structure with superior performance is proposed. The originality consists in the introduction of a low-k spacer that is combined with a high-k gate dielectric. Numerical simulations demonstrate that the use of the low-k spacer and high-k gate dielectric leads to a high on-current, ION, and reduced subthreshold slope. The proposed structure increases ION by a factor of 3.8 and reduces the subthreshold slope by a factor of 2 compared to other structures described in literature.
    Applied Physics Letters 01/2010; 96. · 3.79 Impact Factor
  • T. Chawla, S. Marchal, A. Amara, A. Vladimirescu
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    ABSTRACT: Global and environmental variations including process (P), voltage (V) and temperature (T) constitute the biggest factor among all variations for any ASIC design. The age-old approach of using corners and margins to quantify the impact of variations is still applicable but the increasing margins limit the scaling of max achievable design frequency with technology, especially because of minimum pulse width violation. ASIC designs in current technology are working at these max clock frequencies. Moreover, as the importance of global N-to-P mismatch increases with technology, it increases the sensitivity of clock tree pulse-width to variations. Thus, to continue to scale the clock frequency in the future, we need to make margins and corners that are application specific. In this work, we have estimated the impact of PVT variations on the standard cells in a clock library using industrial models and SPICE simulations. We found that unbalancing the first stage with respect to the pulse edges in a cell reduced the variations by a factor of three without affecting the output behavior. We also found cells with opposite pulse-width variation characteristics enabling their combination in a path to minimize the overall variations.
    Circuits and Systems, 2009. MWSCAS '09. 52nd IEEE International Midwest Symposium on; 09/2009
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    ABSTRACT: This paper presents a comparative study of two novel sub-32 nm current (CSA) and voltage (VSA) sense amplifiers in fully depleted (FD) double-gate (DG) silicon-on-insulator (SOI) technology with planar independent self-aligned gates. The proposed sense amplifiers (SA) need 40% to 4 times less power, achieve a 10-15% increase in speed and have a 2.5 to 5 times larger tolerance to V<sub>th</sub> and L mismatch compared to published DG SAs. Both architectures take advantage of the back gate in order to improve circuit properties. The new CSA is 12% faster and reduces power consumption 3.3 times compared to the new VSA, with the latter having a significant advantage in size.
    Circuits and Systems, 2009. ISCAS 2009. IEEE International Symposium on; 06/2009
  • Tarun Chawla, Sebastien Marchal, Amara Amara, Andrei Vladimirescu
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    ABSTRACT: Local mismatch is one of the challenges facing the microelectronics industry in scaling of transistors. Smaller feature size leads to increased mismatch that causes larger variations in timing properties, which in turn can limit the achievable design frequency or complexity. High speed and low power designs are particularly sensitive to these types of variations. In this work, we have tried to characterize the impact of mismatch in clock networks considering various scenarios and propose a set of guidelines to reduce the probability of timing failures. We have shown that the effect of mismatch is not negligible but it can be reduced to a manageable limit.
    01/2009;
  • Tarun Chawla, Sebastien Marchal, Amara Amara, Andrei Vladimirescu
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    ABSTRACT: Random intra-die variation is an ever-increasing concern in the microelectronics industry. Analysis solutions available today are complex to implement industrially. Most works on intra-die variations concentrate on systematic mismatch that is ameliorated through manufacturing improvements (e.g. regularity improvement in Design Rule Manual). Statistical static timing analysis (SSTA) is said to be a good estimator of random intra-die variations but lacks ease of deployment and requires lots of effort in characterizing the libraries. Even then, extensive analysis tools do not necessarily provide insights about the differences between the impact on various cells and their context. In this work, we have tried to find a rapidly implementable solution in commercial Computer Aided Design (CAD) tools using industrial models to reduce the impact of random intra-die variations at cell level and to find the basic set of parameters on which to base the usability of standard cells. We have characterized the impact of random variations on some basic cells used in clock like structures to achieve the said purpose.
    01/2009;
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    ABSTRACT: This paper describes two novel sub-32 nm current (CSA) and voltage (VSA) sense amplifiers in fully depleted (FD) double-gate (DG) silicon-on-insulator (SOI) technology with planar independent self-aligned gates. The proposed sense amplifiers (SA) need 40% to 4 times less power, achieve a 10-15% increase in speed and have a 2.5 to 3.5 times larger tolerance to Vth and L mismatch compared to published DG SAs. Both architectures take advantage of the back gate in order to improve circuit properties. The new CSA is by 12% faster and reduces power consumption 3.3 times compared to the new VSA, with the latter having a significant advantage in size.
    SOI Conference, 2008. SOI. IEEE International; 11/2008
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    ABSTRACT: This paper introduces a novel voltage sense amplifier (VSA) in fully depleted (FD) double-gate (DG) silicon-on-insulator (SOI) technology with planar independent self-aligned gates. Three different architectures are described and their operation margins are analyzed as a function of transistor length (L) and threshold voltage (Vth) variations and mismatch. The proposed architecture takes advantage of the back gate to enhance feedback and add more input nodes to provide a faster (25%-40%) and more insensitive to mismatch (100%-300%) circuit.
    Electronics, Circuits and Systems, 2008. ICECS 2008. 15th IEEE International Conference on; 10/2008
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    ABSTRACT: This paper introduces a novel current sense amplifier (CSA) in sub-32nm fully depleted (FD) double-gate (DG) silicon-on-insulator (SOI) technology with planar independent self-aligned gates. A new architecture is proposed which takes advantage of the back gate in order to improve circuit properties. Compared to the reference circuit, the new architecture proves to be faster (21% sensing delay decrease), less power consuming (313% power dissipation decrease) and much more resistant to transistor length (L) (125% gain) and threshold voltage mismatches (Vth) (233% gain).
    Integrated Circuit Design and Technology and Tutorial, 2008. ICICDT 2008. IEEE International Conference on; 07/2008
  • B. Giraud, A. Amara, A. Vladimirescu
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    ABSTRACT: This paper presents a comparative study of sub-32 nm CMOS 6T and 4T SRAM cells in fully depleted (FD) double-gate (DG) silicon-on-insulator (SOI) technology with planar independent self-aligned gates. Both independent- and connected-gate operation is analyzed by modulating the drain current with both front and back gate voltages. An improved 4T driver-less (DL) SRAM cell is proposed which takes advantage of the back gate to improve stability in read and retention mode by applying feedback between access transistor and storage node. The results of statistical characterization of read-, retention- and write margins, power and access time are presented for all cells in the presence of process variability.
    Circuits and Systems, 2007. ISCAS 2007. IEEE International Symposium on; 06/2007