-
[show abstract]
[hide abstract]
ABSTRACT: We reviewed 86 cases of human immunodeficiency virus and tuberculosis coinfection; 34.9% were caused by Mycobacterium bovis. Patients with M. bovis infection were more likely to have advanced immunosuppression (CD4 T cell counts ≤200 cells/μL). Hispanic ethnicity, male sex, and abdominal disease were strongly associated with M. bovis disease.
Clinical Infectious Diseases 10/2010; 51(11):1343-6. · 9.15 Impact Factor
-
[show abstract]
[hide abstract]
ABSTRACT: We present an error-tolerant SRAM design optimized for ultra-low standby power. Using SRAM cell optimization techniques, the maximum data retention voltage (DRV) of a 90 nm 26 kb SRAM module is reduced from 550 mV to 220 mV. A novel error-tolerant architecture further reduces the minimum static-error-free V<sub>DD</sub> to 155 mV. With a 100 mV noise margin, a 255 mV standby V<sub>DD</sub> effectively reduces the SRAM leakage power by 98% compared to the typical standby at 1 V V<sub>DD</sub>.
Quality Electronic Design, 2008. ISQED 2008. 9th International Symposium on; 04/2008
-
[show abstract]
[hide abstract]
ABSTRACT: SRAM leakage power dominates the total power of low duty-cycle applications, e.g., sensor nodes. Accordingly, leakage power reduction during data-retention in SRAM standby is often addressed by reducing the supply voltage. Each SRAM cell has a minimum supply voltage parameter called the data-retention voltage (DRV), above which the stored bit can be retained reliably. The DRV exhibits significant intra-chip variation in the deep sub-micron era. As supply voltage is lowered, leakage power reduces, but a larger fraction of SRAM cells is prone to retention failures. Use of appropriate error-correction to mitigate cell- reliability is proposed. Using this approach, the standby supply voltage is selected to minimize leakage power per useful bit. The fundamental limits on the leakage power per useful bit, while taking the DRV distribution into account, are established. Minimization of power per bit results in a supply-voltage at which a small fraction of cells fail to retain the data. For experimental DRV -distributions, a [31,26,3] Hamming code based implementation achieves a significant portion of the leakage power reduction compared to the fundamental limit. These analytical results are verified by twenty-four experimental chips manufactured in an industrial 90 nm CMOS process.
Quality Electronic Design, 2008. ISQED 2008. 9th International Symposium on; 04/2008
-
J. Low Power Electronics. 01/2006; 2:401-411.
-
[show abstract]
[hide abstract]
ABSTRACT: Design challenges for operating CMOS circuits fabricated in 0.13 μm and finer technologies at ultra-low-voltages are analyzed. The design goal consists in minimizing energy by reducing V<sub>DD</sub> while maintaining delay and yield at acceptable levels in the presence of increasing variability of process parameters. First, an estimation model developed to accurately predict operation of bulk- and SOI-CMOS in subthreshold is described. The relation between yield, energy, delay and device parameter distributions is examined next along with tradeoffs necessary to achieve the desired performance point. The main objective of minimizing energy is explored for SRAM cells by predicting the minimum V<sub>DD</sub> based on the data-retention voltage (DRV), and acceptable signal-to-noise margins (SNM). Experimental data from a 4 kB-SRAM test chip in 0.13 μm CMOS are presented demonstrating a 90% leakage reduction potential in standby under reduced bias of 250 mV.
Circuits and Systems, 2004. NEWCAS 2004. The 2nd Annual IEEE Northeast Workshop on; 07/2004
-
[show abstract]
[hide abstract]
ABSTRACT: As circuit parametric variations aggravate in advanced technology, yield emerges as an important figure-of-merit in circuit design. Based on a 130 nm technology, the yield-energy-delay tradeoffs in low-power circuit optimization are investigated. Using a log-normal statistical model, Monte-Carlo analyses are performed on typical circuit examples, including an inverter chain, NAND gate, and 4-bit adder. While energy reduction can be effectively achieved by tuning supply voltage (V<sub>dd</sub>), threshold voltage (V<sub>th</sub>), and device width (W), circuit yield degrades during this process. On the other hand, it is observed that performance variability is relatively insensitive to circuit topology and device length (L). Design guidelines for optimizing yield in the presence of parametric variations and energy-delay constraints are proposed.
Electron Devices and Solid-State Circuits, 2003 IEEE Conference on; 01/2004
-
5th International Symposium on Quality of Electronic Design (ISQED 2004), 22-24 March 2004, San Jose, CA, USA; 01/2004
-
[show abstract]
[hide abstract]
ABSTRACT: Suppressing the leakage current in memories is critical in low-power design. By reducing the standby supply voltage (VDD) to its limit, which is the data retention voltage (DRV), leakage power can be substantially reduced. This paper models the DRV of a standard low leakage SRAM module as a function of process and design parameters, and analyzes the SRAM cell stability when VDD approaches DRV. The DRV model is verified using simulations as well as measurements from a 4 KB SRAM chip in a 0.13 μm technology. Due to a large on-chip variation, DRV of the 4 KB SRAM module ranges between 60 and 390 mV. Measurements taken at 100 mV above the worst-case DRV show that reducing the SRAM standby VDD to a safe level of 490 mV saves 85% leakage power. Further savings can be achieved by applying DRV-aware SRAM optimization techniques, which are discussed at the end of this paper.
Microelectronics Journal.
