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ABSTRACT: This paper presents a geometry-scalable parasitic deembedding technique for on-wafer S -parameter measurements of silicon MOSFETs. The proposed methodology is based on the transmission-line theory and the cascade and parallel combinations of two-port networks. We use only one ¿reflect¿ and one ¿thru¿ dummy structure on a wafer to remove the feeding networks with arbitrary geometry surrounding the MOS transistors. The shielding technique is employed to improve the substrate isolation and fixture scalability. To mitigate the parasitic effects of the dangling leg between the MOSFET and the ground plane, microstriplike interconnects are introduced to mount the devices. Full-wave electromagnetic simulations were also accomplished to substantiate the interconnect scalability and network combinations. The MOS transistors and deembedding dummy patterns were implemented in a 0.13-¿m standard CMOS technology and characterized up to 30 GHz. Compared with the conventional deembedding methods, the proposed approach consumes less than 33% of chip area and characterization time for modeling test keys, while still maintaining high accuracy.
IEEE Transactions on Electron Devices 03/2009; · 2.32 Impact Factor
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ABSTRACT: In this brief, a miniature test structure for RF device characterization and process monitoring has been proposed. This new layout design can minimize the voltage drop across interconnects and can prevent capacitive coupling to devices. It consumes only 36% and 40% of the chip area of the conventional on-wafer and in-line test structures, respectively. The RF characteristics of the proposed test structure are shown to be in excellent agreement with those of the conventional ones.
IEEE Transactions on Electron Devices 02/2008; · 2.32 Impact Factor
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ABSTRACT: In this paper, the power gain, power-added efficiency (PAE) and linearity of power SiGe heterojunction-bipolar transistors at various temperatures have been presented. The power characteristics were measured using a two-tone load-pull system. For transistors biased with fixed base voltage, the small-signal power gain and PAE of the devices increase with increasing temperature at low base voltages, while they decrease at high base voltages. Besides, the linearity is improved at high temperature for all voltage biases. However, for devices with fixed collector current, the small-signal power gain, PAE, and linearity are nearly unchanged with temperature. The temperature dependence of power and linearity characteristics can be understood by analyzing the cutoff frequency, the collector current, Kirk effect and nonlinearities of transconductance at different temperatures.
IEEE Transactions on Electron Devices 08/2005; · 2.32 Impact Factor
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IEICE Transactions. 01/2005; 88-C:845-850.
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Microwave Conference, 2004. 34th European; 11/2004
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ABSTRACT: In this paper, the linear power gain, gain expansion and gain compression of power SiGe HBTs at various temperatures have been presented. At low base voltage, the linear power gain increases with increasing temperature, while the linear power gain decreases at high base voltage. Besides we observe the gain expansion will exist as base voltage is in low value, but it will disappear when the temperature increases to 75°C. After gain compression, the power gain increases with increasing temperature no matter what the base voltage is. We explain this phenomenon by analyzing the cutoff frequency and the collector current at different temperatures.
Microwave Symposium Digest, 2004 IEEE MTT-S International; 07/2004
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ABSTRACT: This paper presents a general S-parameter de-embedding method using only one "OPEN" and one "THRU" dummy structures for on-wafer microwave characterization and automatic measurement. By aggressively combining the transmission-line theory and cascade-configuration concept, this method can efficiently create the scalable and repeatable interconnect parameters to accurately eliminate the redundant parasitics of the device-under-test (DUT). With the application of the proposed technique, both active and passive devices, such as MOSFET, BJT, spiral inductor, and MIM capacitor, can be de-embedded to acquire their intrinsic performances, and the consumption of chip area for on-wafer device characterization can be significantly saved.
Microwave Symposium Digest, 2004 IEEE MTT-S International; 07/2004
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ABSTRACT: This paper presents the temperature effects on the performance of 4-port transformer. The transformer is fabricated on the silicon substrate using 0.18 μm CMOS process technique measured and characterised over the temperature range from -30 °C to 125 °C. At lower frequencies the effective resistance is dominated with metal resistance and increases with increasing temperature due to positive resistivity temperature coefficient of the metal trace. Magnetic coupling (K), mutual-inductance (M) and quality factor (Q) versus frequency curves for one winding of the transformer at different temperatures shows that at higher frequencies, neither M nor L dominate magnetic coupling (K).
Semiconductor Device Research Symposium, 2003 International; 01/2004
