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ABSTRACT: Positive bias and temperature (PBTI) stress induced drain current degradation in HfSiON gate dielectric nMOSFETs is investigated by using a transient measurement technique. The degradation exhibits two stages, featuring different degradation rate and stress temperature dependence. The drain current degradation in the first stage is attributed to the charging of pre-existing high-k dielectric traps while the degradation in the second stage is mainly due to additional high-k trap creation. Process effect on high-k trap growth is evaluated
Electron Devices Meeting, 2005. IEDM Technical Digest. IEEE International; 01/2006
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ABSTRACT: A novel method to study post-NBTI stress recovery in pMOSFETs is demonstrated by direct measurement of single-hole de-trapping behavior. Individual trapped hole emission in NBTI recovery is observed for the first time, which is manifested by the step-like evolution of channel current. By measuring trapped hole emission times and corresponding current jump, the dependence of NBTI recovery on stress hardness, recovery gate voltage and temperature, and gate length is characterized. An analytical model based on thermally-assisted tunneling of trapped oxide charges can successfully reproduce measured recovery characteristics.
VLSI Technology, 2005. Digest of Technical Papers. 2005 Symposium on; 07/2005
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Reliability Physics Symposium, 2005. Proceedings. 43rd Annual. 2005 IEEE International; 02/2005
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ABSTRACT: Enhanced oxide breakdown progression in ultra-thin oxide silicon-on-insulator p-type metal-oxide-semiconductor field-effect transistors is observed, as compared to bulk devices. The enhanced progression is attributed to the increase of hole stress current resulting from breakdown induced channel carrier heating in a floating-body configuration. Numerical analysis of hole tunneling current and hot carrier luminescence measurement are performed to support our proposed theory. This phenomenon is particularly significant to the reliability of devices with ultra-thin oxides and low operation gate voltage.
Journal of Applied Physics 09/2004; 96(6):3473-3477. · 2.17 Impact Factor
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ABSTRACT: The impact of oxide soft breakdown location on threshold voltage hysteresis in partially depleted silicon-on-insulator metal-oxide-semiconductor field effect transistors with an ultrathin oxide (1.6 nm) is investigated. Two breakdown enhanced hysteresis modes are identified. In a drain-edge breakdown device, excess holes result from band-to-band tunneling flow to the floating body, thus causing threshold voltage variation in drain bias switching. In contrast, in a channel breakdown device, enhanced threshold hysteresis is observed during gate bias switching because of increased valence band electron tunneling. Our findings reveal that soft breakdown enhanced hysteresis effect can be a serious reliability issue in silicon-on-insulator devices with floating body configuration.
Journal of Applied Physics 08/2004; 96(4):2297-2300. · 2.17 Impact Factor
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C.T. Chan,
C.H. Kuo,
C.J. Tang,
M.C. Chen,
T. Wang,
S.H. Lu,
H.C. Hu,
T.F. Chen,
C.K. Yang,
M.T. Lee,
D.Y. Wu,
J.K. Chen,
S.C. Chien,
S.W. Sun
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ABSTRACT: Accelerated oxide breakdown progression in ultra-thin oxide (1.4 nm) SOI pMOSFETs is observed, as compared to bulk devices. The accelerated progression is explained by the increase of hole stress current as a result of breakdown induced channel carrier heating in a floating-body configuration. Numerical simulation of hole tunneling current and hot carrier luminescence measurement are carried out to justify the proposed theory.
Physical and Failure Analysis of Integrated Circuits, 2004. IPFA 2004. Proceedings of the 11th International Symposium on the; 08/2004
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ABSTRACT: The lateral distribution of programmed charge in a hot electron program/hot hole erase nitride storage flash cell is investigated by using a charge pumping technique. Our study shows that the secondly programmed bit has a wider trapped charge distribution than the first programmed bit. In addition, we find programmed charge spreads further into the channel with program/erase cycle number.
Reliability Physics Symposium Proceedings, 2004. 42nd Annual. 2004 IEEE International; 05/2004
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ABSTRACT: The reliability issues of two-bit storage nitride flash memory cells, including low-V<sub>t</sub> state threshold voltage instability, read-disturb, and high-V<sub>t</sub> state charge loss are addressed. The responsible mechanisms and reliability models are discussed. Our study shows that the cell reliability is strongly dependent on operation methods and process conditions.
Electron Devices Meeting, 2003. IEDM '03 Technical Digest. IEEE International; 01/2004
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ABSTRACT: Negative substrate bias enhanced breakdown hardness in ultra-thin oxide (1.4 nm) pMOS is observed. This result is believed to be due to the increase of hole stress current during breakdown progression via breakdown induced carrier heating. Numerical analysis of the substrate bias effect on hole tunneling current is performed to support the proposed theory. This phenomenon is particularly significant to gate oxide reliability in floating substrate (PD-SOI) or forward-biased substrate devices.
Reliability Physics Symposium Proceedings, 2003. 41st Annual. 2003 IEEE International;
