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V. Subramanian
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ABSTRACT: There has been significant interest in the applications of printed electronics in the realization of fully-printed RFID tags and embedded sensors. Printing of active circuitry is expected to enable a dramatic reduction in the overall cost of these systems, allowing for integration of electronic barcodes and product quality detection systems into consumer goods. In this talk, I will review our work on developing materials, processes, devices, and circuit architectures for all-printed RFID and tags, and, based on these results, will evaluate the likely system constraints that will define such fully printed systems. We have already realized a full range of printable transistors, diodes, passive components, and memories suitable for use in RFID applications. Performance of these components is rapidly approaching the requisite levels for realization of simple RF Barcodes. Based on robust models we have developed for our devices, I will review the circuit implications of the same and will review the likely topology and performance limits associated with fully printed RFID. Furthermore, I will review or work on developing a range of chemical and biosensors for use in low cost product quality monitoring and biosensing applications.
Microelectronics and Electron Devices, 2008. WMED 2008. IEEE Workshop on; 05/2008
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ABSTRACT: We report an OTFT-based label-free DNA hybridization detection system integrating electrically-read DNA hybridization sensors and microfluidic delivery channels. We use DNA-doped OTFTs as electrically-read DNA sensors. By integrating with polymer microfluidics, for the first time, we demonstrate the technologies required to realize disposable, rapid turn-around tools for field-deployable genetic diagnosis.
Electron Devices Meeting, 2007. IEDM 2007. IEEE International; 01/2008
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ABSTRACT: Solution-processed transparent zinc oxide (ZnO) transistors are demonstrated using a chemical bath deposition process for ZnO deposition. The process is glass compatible and amenable to producing fully transparent electronics. Mobility as high as 3.5 cm<sup>2</sup>/V ldr s with on-off ratios of ~10<sup>5</sup> is realized. The transparency of ZnO allows for complete coverage of the pixel by the pixel drive transistors; analysis shows that the performance achieved herein is sufficient even to drive high-brightness organic light-emitting diode (OLED) displays by exploiting the high mobility and optical transparency of these devices. This makes this technology extremely attractive for use in active-matrix OLED display applications.
IEEE Transactions on Electron Devices 07/2007; · 2.32 Impact Factor
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ABSTRACT: Crystalline monolayer films of a novel organic semiconducting material were deposited as the active layer for organic thin-film transistors (OTFTs) via inkjet printing. Devices exhibited field-effect mobilities up to 0.07 cm<sup>2</sup>/V·s and on/off ratios >10<sup>8</sup>, surpassing values measured for devices cast with thicker films of the same material. The printed monolayer devices exhibited superior subthreshold characteristics with less hysteresis, and defect and trap densities are improved over thicker film analogs. These results show that solution deposition techniques such as inkjet printing can result in the monolayer crystalline thin films that are requisite for near-ideal electrostatics in OTFTs.
IEEE Transactions on Electron Devices 05/2006; · 2.32 Impact Factor
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ABSTRACT: Printed electronics holds promise for realizing ultra-low-cost RFID tags for item-level tracking of consumer goods. We report on our progress in developing all-printed RFID tags. We review the development of printable materials for these applications, summarize the characteristics of printed devices, and discuss the implications of these on circuit performance limits and needs. Based on this assessment, we discuss the outlook for all-printed RFID tags and identify the problems remaining to be solved and the efforts taking place in this regard.
VLSI Design, 2006. Held jointly with 5th International Conference on Embedded Systems and Design., 19th International Conference on; 02/2006
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ABSTRACT: We demonstrate printed organic transistors with sub-10V V<sub>DD </sub>. Using inkjetted nanoparticle conductors, a polymer dielectric, and a pentacene precursor semiconductor, we demonstrate devices on plastic with mobilities >0.05cm<sup>2</sup>/V-s and on-off ratios >10<sup>5</sup>. Thus, for the first time, we demonstrate devices with operating specifications approaching those required for low-cost electronic systems
Electron Devices Meeting, 2005. IEDM Technical Digest. IEEE International; 01/2006
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ABSTRACT: Printed electronics provides a potential pathway toward the realization of ultra-low-cost radio frequency identification (RFID) tags for item-level tracking of consumer goods. Here, we report on our progress in developing materials and processes for the realization of printed transistors for low-cost RFID applications. Using inkjet printing of novel conductors, dielectrics, and organic semiconductors, we have realized printed transistors with mobilities >10<sup>-1</sup>cm<sup>2</sup>/V-s. AC performance of these devices is adequate for 135-kHz RFID, and, with further optimization, 13.56-MHz RFID appears to be within reach. We review the performance of these devices, and discuss optimization strategies for achieving the ultimate performance goals requisite for realizing ultra-low-cost printed RFID.
IEEE Transactions on Components and Packaging Technologies 01/2006; · 0.94 Impact Factor
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ABSTRACT: Organic thin-film transitors (OTFTs) were fabricated with channel lengths as small as 10 nm and an operating voltage of V<sub>DD</sub>=-0.3 V using e-beam lithography. For sub-200-nm channel lengths, scaling L downwards resulted in increased on-current, decreased I<sub>on</sub>/I<sub>off</sub> ratio, V<sub>T</sub>-rolloff, and drain-induced barrier lowering. These trends are correlated with device topology, electrostatics, and thin-film morphology. Nanoscale OTFT are interesting both as a means of studying intrinsic electrical properties of organic materials and as a possible route toward increasing on-current in organic devices. This paper sheds light on many of the issues encountered when shrinking organic devices, providing insight into approaches for optimizing nanoscaled OTFT.
IEEE Transactions on Electron Devices 09/2005; · 2.32 Impact Factor
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ABSTRACT: Printed electronics provides a promising potential pathway toward the realization of ultralow-cost RFID tags for item-level tracking of consumer goods. Here, we report on our progress in developing materials, processes, and devices for the realization of ultralow-cost printed RFID tags. Using printed nanoparticle patterns that are subsequently sintered at plastic-compatible temperatures, low-resistance interconnects and passive components have been realized. Simultaneously, printed transistors with mobilities >10<sup>-1</sup> cm<sup>2</sup>/V-s have been realized using novel pentacene and oligothiophene precursors for pMOS and ZnO nanoparticles for nMOS. AC performance of these devices is adequate for 135-kHz RFID, though significant work remains to be done to achieve 13.56-MHz operation.
Proceedings of the IEEE 08/2005; · 6.81 Impact Factor
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ABSTRACT: Flexible transistors were formed directly on fibers in a novel weave-masking fabrication process. Pentacene fiber transistors exhibit mobilities of >0.5 cm<sup>2</sup>/V-s measured at 20 V V<sub>DD</sub> and operate stably under a wide range of flexion stress. Devices are defined and positioned solely by a weaving pattern, meaning that simple circuits could potentially be directly built into fabric during manufacturing. This development offers a novel approach for providing information routing within fabric, which is currently a major hurdle in electronic textile development.
IEEE Transactions on Electron Devices 03/2005; · 2.32 Impact Factor
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Device Research Conference Digest, 2005. DRC '05. 63rd; 02/2005
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ABSTRACT: An all ink-jet-deposited process capable of creating high-quality passive devices suitable for an RFID front-end is described. Gold nanocrystals are printed to create conductive lines with sheet resistance as low as 23 mΩ per square. Optimal printing conditions are found for polyimide dielectric layers and films as thin as 340 nm are produced. These results are used to create spiral inductors, interconnect, and parallel plate capacitors.
IEEE Transactions on Electron Devices 01/2005; · 2.32 Impact Factor
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ABSTRACT: Through the use of a novel oligothiophene precursor, we have demonstrated organic TFTs exhibiting relatively high mobility while simultaneously retaining ultra-low leakage and excellent on-off ratios. The unique tendency of this material to self-assemble into a crystalline morphology allows non-uniform printed droplets to reorganize into high-quality monolayers. The resulting structure provides excellent electrostatic characteristics, ideal for low power analog applications.
Device Research Conference, 2004. 62nd DRC. Conference Digest [Includes 'Late News Papers' volume]; 07/2004
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ABSTRACT: For the first time, we demonstrate flexible transistors formed directly on fibers. This represents a significant step towards the realization of electronics textiles. Fiber transistors exhibit mobilities of >10<sup>-2</sup> cm<sup>2</sup>/V-s measured at 20 V V<sub>DD</sub>. The entire transistor is fabricated without resorting to conventional lithography techniques. Patterning is achieved via shadowing from overwoven fibers. The process is compatible with textile manufacturing, and is therefore a promising technology for scalable e-textile fabrication.
Electron Devices Meeting, 2003. IEDM '03 Technical Digest. IEEE International; 01/2004
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ABSTRACT: In this paper, we demonstrate an all-printed passive component technology on plastic, including inductors, capacitors, and multilevel interconnects. This represents an important step towards the development of ultra-low-cost RFID on plastic.
Device Research Conference, 2003; 07/2003
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ABSTRACT: This work summarizes the results of several experiments to investigate the potential applications of Silicon-Germanium alloy in the fabrication of shallow source/drain (S/D) extension Junctions for deep submicron PMOS transistors. Two approaches were used for the fabrication of p<sup>+</sup>-Si<sub>1-x</sub>Ge<sub>x</sub>/n-Si heterojunctions. In the first approach, high dose Ge ion implantation followed by boron implantation into Si was used to form very shallow p<sup>+</sup>-Si<sub>1-x</sub>Ge<sub>x</sub>/n-Si junctions (x≤0.2). In the second approach, thin Ge films were deposited onto Si substrates by conventional low pressure chemical vapor deposition. This was followed by boron implantation into the Ge and thermal annealing to co-diffuse Ge and B atoms into Si and form p<sup>+</sup>/n heterojunctions. The electrical characteristics of the heterojunction diodes were comparable to those of conventional Si (homo) junctions. Secondary ion mass spectrometry (SIMS) concentration-depth profiles indicate that dopant segregation in the Si<sub>1-x</sub>Ge<sub>x</sub> regions resulted in the formation of ultra-shallow and abrupt junctions that could be used as S/D extensions for sub-100 nm CMOS generations. PMOS transistors fabricated using these techniques exhibit superior short-channel performance compared to control devices, for physical gate lengths down to 60 nm.
IEEE Transactions on Electron Devices 09/2002; · 2.32 Impact Factor
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ABSTRACT: Driven by strain relaxation, the rapid thermal annealing (RTA) of B-doped Ge on an Si substrate forms graded Si/sub 1-x/Ge/sub x/ layers with B confined inside. Based on this observation of Ge-B/Si intermixing, a novel elevated source/drain (S/D) PMOSFET fabrication process is proposed. The new process consists of three simple steps: (a) selective Ge deposition in S/D regions by conventional LPCVD, (b) B implantation, and (c) RTA for Ge-B/Si intermixing to form S/D extensions to the channel. Fabricated PMOSFETs with sub-100 nm gate lengths display excellent short channel performance.
IEEE Electron Device Letters 05/2002; · 2.85 Impact Factor
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ABSTRACT: Thin-body p-channel MOS transistors with a SiGe/Si heterostructure
channel were fabricated on silicon-on-insulator (SOI) substrates. A
novel lateral solid-phase epitaxy process was employed to form the
thin-body for the suppression of short-channel effects. A selective
silicon implant that breaks up the interfacial oxide was shown to
facilitate unilateral crystallization to form a single crystalline
channel. Negligible threshold voltage roll-off was observed down to a
gate length of 50 nm. The incorporation of Si<sub>0.7</sub>Ge<sub>0.3
</sub> in the channel resulted in a 70% enhancement in the drive
current. This is the smallest SiGe heterostructure-channel MOS
transistor reported to date. This is also the first demonstration of a
thin-body MOS transistor incorporating a SiGe heterostructure channel
IEEE Transactions on Electron Devices 03/2002; · 2.32 Impact Factor
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Xuejue Huang,
Wen-Chin Lee,
C. Kuo,
D. Hisamoto,
Leland Chang,
J. Kedzierski,
E. Anderson,
H. Takeuchi,
Yang-Kyu Choi,
K. Asano, V. Subramanian,
Tsu-Jae King,
J. Bokor,
Chenming Hu
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ABSTRACT: High-performance PMOSFETs with sub-50-nm gate-length are reported.
A self-aligned double-gate MOSFET structure (FinFET) is used to suppress
the short-channel effects. This vertical double-gate SOI MOSFET
features: 1) a transistor channel which is formed on the vertical
surfaces of an ultrathin Si fin and controlled by gate electrodes formed
on both sides of the fin; 2) two gates which are self-aligned to each
other and to the source/drain (S/D) regions; 3) raised S/D regions; and
4) a short (50 nm) Si fin to maintain quasi-planar topology for ease of
fabrication. The 45-nm gate-length p-channel FinFET showed an I<sub>dsat
</sub> of 820 μA/μm at V<sub>ds</sub>=V<sub>gs</sub>=1.2 V and T
<sub>ox</sub>=2.5 mm. Devices showed good performance down to a
gate-length of 18 nm. Excellent short-channel behavior was observed. The
fin thickness (corresponding to twice the body thickness) is found to be
critical for suppressing the short-channel effects. Simulations indicate
that the FinFET structure can work down to 10 nm gate length. Thus, the
FinFET is a very promising structure for scaling CMOS beyond 50 nm
IEEE Transactions on Electron Devices 06/2001; · 2.32 Impact Factor
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ABSTRACT: Summary form only given. The quasi-planar FinFET structure has
device characteristics similar to those of the conventional MOSFET.
Inserting FinFET into CMOS technology requires no change in circuit
architecture or layout/design tools, providing a smooth transition to
post-planar CMOS technology. 2D mixed-mode simulations show FinFET
circuit performance exceeds that of advanced single gate MOSFETs
Solid-State Circuits Conference, 2001. Digest of Technical Papers. ISSCC. 2001 IEEE International; 02/2001
