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S. Seo,
L.F. Edge,
S. Kanakasabapathy,
M. Frank,
A. Inada,
L. Adam,
M.M. Wang,
K. Watanabe, P. Jamison,
K. Ariyoshi, [......],
S.L. Brown,
J. Chang,
E.A. Cartier,
D. Park,
J.H. Stathis,
B. Doris,
R. Divakaruni,
M. Khare,
V. Narayanan,
V.K. Paruchuri
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ABSTRACT: Tungsten-based full metal gate (FMG) stacks that are equivalent to or better than metal-inserted poly-Si (MIPS) stack have been developed. These fully encapsulated FMG stacks enable borderless source/drain contacts needed for the 14 nm technology node and beyond, where the contacted gate pitch is expected to be less than 80 nm. Tungsten replaces gate salicidation with the sheet resistance ≤ 14 Ω/□. FMG stack show excellent Tinv scaling (0.92 and 1.15 nm for NFET and PFET, respectively) and enhanced hole mobility by 20% compared to MIPS gate stack. Fully integrated short channel devices and borderless contacts are demonstrated at 80 nm contacted gate pitch.
VLSI Technology (VLSIT), 2011 Symposium onVLSI Technology (VLSIT), 2011 Symposium on; 01/2011
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K. Choi,
H. Jagannathan,
C. Choi,
L. Edge,
T. Ando,
M. Frank, P. Jamison,
M. Wang,
E. Cartier,
S. Zafar,
J. Bruley,
A. Kerber,
B. Linder,
A. Callegari,
Q. Yang,
S. Brown,
J. Stathis,
J. Iacoponi,
V. Paruchuri,
V. Narayanan
[show abstract]
[hide abstract]
ABSTRACT: We report for the first time that extreme EOT scaling and low n/p VTHs can be achieved simultaneously. Underlying mechanisms that enable EOT scaling and EWF tuning are explained and the fundamental device parameters including reliability of the extremely scaled devices are discussed. Record low gate leakage, appropriately low V<sub>TH</sub>s and competitive carrier mobilities in this work demonstrate the gate stack technology that is consistent with the sub-22 nm node requirements.
VLSI Technology, 2009 Symposium on; 07/2009
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V. Narayanan,
K. Maitra,
B.P. Linder,
V.K. Paruchuri,
E.P. Gusev, P. Jamison,
M.M. Frank,
M.L. Steen,
D. La Tulipe,
J. Arnold,
R. Carruthers,
D.L. Lacey,
E. Cartier
[show abstract]
[hide abstract]
ABSTRACT: The performance of aggressively scaled (1.4nm<T<sub>inv</sub><2.1nm) self-aligned HfO<sub>2</sub>-based nMOSFETs with various metal gate electrodes (W, TaN, TiN, and TaSiN) is optimized. It is shown that high mobility values, competitive with oxynitride controls (SiON/poly-Si, T<sub>inv</sub>∼1.8-2.1nm), can be achieved. Detailed studies of the role of interface states, remote charges in the HfO<sub>2</sub> layer, interfacial layer regrowth, and nitrogen-induced charge lead to the conclusion that high-temperature-induced structural modifications near the SiO<sub>2</sub>/HfO<sub>2</sub> interface substantially improve the electron mobility.
IEEE Electron Device Letters 08/2006; · 2.85 Impact Factor
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[show abstract]
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ABSTRACT: We report chemical interactions of Hf-based dielectrics with Re and Pt overlayers during annealing. Reduction of the Hf to a suboxide is observed by x-ray photoelectron spectroscopy, along with a decrease in total oxygen content measured by medium-energy ion scattering. For Re, this unanticipated reaction is highly dependent on the premetallization history of the sample. The presence of hydroxyl groups, observed by infrared absorption, is thought to be responsible. In addition, substantial electrostatic core-level shifts are observed, even in the absence of Hf reduction. The electrostatic shifts are symptomatic of altered threshold voltages for devices.
Applied Physics Letters 02/2006; 88(7):072914-072914-3. · 3.84 Impact Factor
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Y.H. Kim,
C. Cabral,
E.P. Gusev,
R. Carruthers,
L. Gignac,
M. Gribelyuk,
E. Cartier,
S. Zafar,
M. Copel,
V. Narayanan,
J. Newbury,
B. Price,
J. Acevedo, P. Jamison,
B. Linder,
W. Natzle,
J. Cai,
R. Jammy,
M. Ieong
[show abstract]
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ABSTRACT: We present a systematic examination of work function modulation and scavenging effect on fully silicided gates using different NiSi alloys (Ti, Hf, Zr, Pd, Pt, and Al) as well as different phases (Ni<sub>31</sub>Si<sub>12</sub> and Ni<sub>rich</sub>-Pt-Si). It is shown that the interface layer between gate FUSI and dielectric is the key to modulate the work function. FUSI alloys were able to prevent Fermi level pining on HfSiO and HfO<sub>2</sub> by modification of the top interface. A ~400 meV work function shift was achieved toward the conduction band edge using NiAlSi demonstrating a mobility of 300 cm<sub>2</sub>/Vs at peak, matching NiSi control devices on Hf<sub>x </sub>SiO<sub>y</sub>. Interface engineering with FUSI alloy gate has not only shown threshold voltage modulation but also enabled further gate oxide scaling (0.15 ~ 0.2nm) compared to NiSi control device. Additional gate oxide scaling is due to the increase of effective dielectric constant in the FUSI gate stack. TEM, EELS, and EDX showed that work function modulation is attributed to the Al pile up at interface. Ni rich silicide FUSI gates showed a ~250mV shift from mid gap toward valence band edge with elimination of Fermi-level pining by modification of the top dielectric interface
Electron Devices Meeting, 2005. IEDM Technical Digest. IEEE International; 01/2006
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[show abstract]
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ABSTRACT: We report the following results for metal/HfO<sub>2</sub>/oxide stacks, (i) The energy level band diagram of HfO<sub>2</sub>/SiO<sub>2</sub> stacks is experimentally determined for the first time; the conduction band offset between HfO<sub>2</sub> and interfacial SiO<sub>2</sub> is estimated to be 2.05 eV. (ii) Work functions of W, Re and TaSiN are measured for HfO<sub>2</sub>/SiO<sub>2</sub>/Si and SiO<sub>2</sub>/Si stacks: work functions exhibit no Fermi pinning effect in HfO<sub>2</sub>, unlike previous report by Schaeffer et al in 2004. (iii) The impact of metal gate deposition on its work function and the oxide charge density is investigated. Measurements show that the tungsten work function is independent of deposition time and method (CVD vs. sputtering). However, oxide charge density (Q<sub>0X</sub>) depends both on the deposition time and method: Q<sub>0X</sub> is positively charged for CVD and negatively charged for sputtered depositions. Also, Q<sub>0X</sub> increases with W deposition time.
VLSI Technology, 2005. Digest of Technical Papers. 2005 Symposium on; 07/2005
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E. Cartier,
F.R. McFeely,
V. Narayanan, P. Jamison,
B.P. Linder,
M. Copel,
V.K. Paruchuri,
V.S. Basker,
R. Haight,
D. Lim,
R. Carruthers,
T. Shaw,
M. Steen,
J. Sleight,
J. Rubino,
H. Deligianni,
S. Guha,
R. Jammy,
G. Shahidi
[show abstract]
[hide abstract]
ABSTRACT: We demonstrate experimentally that the flatband/threshold voltages (V<sub>FB</sub>/V<sub>t</sub>) of pFET metal gates are strongly dependent on the post-deposition annealing conditions of the gate stacks. By varying the temperature and the O<sub>2</sub> partial pressure during post-deposition N<sub>2</sub>/O<sub>2</sub> and/or forming gas annealing (FGA) with Re, Ru and Pt, the gate stack V<sub>FB</sub> can change by as much as 750 mV. However, using Re as an example, it is shown that conditions can be optimized and V<sub>FB</sub>/V<sub>t</sub>-tuning for pFETs can be achieved for aggressively scaled stacks. It is proposed that charge transfer from oxygen vacancies to the gate electrode, possible only for high workfunction metal gates, leads to the formation of a dipole layer near the gate which can shift V<sub>FB</sub>/V<sub>t</sub>. The results indicate that V<sub>FB</sub>/V<sub>t</sub> control remains a formidable processing challenge with high workfunction metals on HfO<sub>2</sub>.
VLSI Technology, 2005. Digest of Technical Papers. 2005 Symposium on; 07/2005
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B. Doris,
D.G. Park,
K. Settlemyer, P. Jamison,
D. Boyd,
Y. Li,
J. Hagan,
T. Staendert,
J. Mezzapelli,
D. Dobuzinsky,
B. Linder,
V. Narayanan,
S. Callegari,
E. Gousev,
K. Guarini,
R. Jammy,
M. Leong
[show abstract]
[hide abstract]
ABSTRACT: We have demonstrated aggressively scaled high performance UTSOI replacement gate CMOS featuring a HfO<sub>2</sub>/TaN gate stack which achieves T<sub>inv</sub> of 17.5nm with greater than 100 times reduction in leakage compared to a SiON/poly-Si control sample. The atomic layer deposition process, used for the metal gate electrode material, enables the replacement gate structure to be robust at extremely small dimensions. An offset spacer together with the ultra-thin Si channel is used to demonstrate functional sub-25nm UTSOI replacement gate pFETs with high-k and metal gate for the first time. These results suggest that the replacement gate architecture is a viable option for future high performance CMOS technologies.
VLSI Technology, 2005. (VLSI-TSA-Tech). 2005 IEEE VLSI-TSA International Symposium on; 05/2005
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E.P. Gusev,
V. Narayanan,
S. Zafar,
C. Cabral Jr,
E. Carrier,
N. Bojarczuk,
A. Callegari,
R. Carruthers,
M. Chudzik,
C. D'Emic,
E. Duch, P. Jamison,
P. Kozlowski,
D. LaTulipe,
K. Maitra,
F.R. McFeely,
J. Newbury,
V. Paruchuri,
M. Steen
[show abstract]
[hide abstract]
ABSTRACT: A comparative analysis of charge trapping in advanced metal gate/high-k stacks with EOT below 1 nm (corresponding to CETs, or T<sub>inv</sub>, in the 1.2-1.5 nm range) has been carried out. We investigate the effects of: (i) gate electrode material (namely, various metals vs. fully silicided gates (FUSI) vs. conventional poly-Si gates); (ii) high-k dielectric material (HfO<sub>2</sub>, HfO<sub>2</sub>:N, HfSiO, HfSiON, ZrO<sub>2</sub>, Al<sub>2</sub>O<sub>3</sub>); (iii) high-k deposition technique (MOCVD vs. ALD); (iv) bottom interface; and (v) annealing effects, both postdeposition (PDA) and in a forming gas (FGA). Significant improvement of charge trapping in all Me-gate stacks has been consistently demonstrated. Based on this systematic analysis, we come to a conclusion that interaction(s) between the high-k layer and poly-Si plays a major role in charge trapping degradation.
Electron Devices Meeting, 2004. IEDM Technical Digest. IEEE International; 01/2005
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A. Callegari, P. Jamison,
E. Carrier,
S. Zafar,
E. Gusev,
V. Narayanan,
C. D'Emic,
D. Lacey,
F.M. Feely,
R. Jammy,
M. Gribelyuk,
J. Shepard,
W. Andreoni,
A. Curioni,
C. Pignedoli
[show abstract]
[hide abstract]
ABSTRACT: Electron mobilities of W/HfO<sub>2</sub> stacks were found to increase monotonically with annealing temperature with little (peak) or no degradation (1 MV/cm) when compared to poly-Si devices using conventional oxides. For stacks annealed at high temperature charge pumping curves indicate low interface states densities of ∼5 × 10<sup>10</sup> charges/cm<sup>2</sup>. Mobility enhancement can also be attributed to a structural change in the HfO<sub>2</sub> gate stack rather than due to only interfacial layer re-growth.
Electron Devices Meeting, 2004. IEDM Technical Digest. IEEE International; 01/2005
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Huiling Shang,
J.O. Chu,
S. Bedell,
E.P. Gusev, P. Jamison,
Ying Zhang,
J.A. Ott,
M. Copel,
D. Sadana,
K.W. Guarini,
Meikei Ieong
[show abstract]
[hide abstract]
ABSTRACT: For the first time, we have integrated strained germanium (s-Ge) channel PMOSFETs with conventional CMOS processes including shallow trench isolation (STI) and scaled thin gate dielectrics. The selectively formed thin s-Ge channels are realized on pre-patterned SiGe on insulator (SGOI) regions by local thermal mixing (TM) or selective UHVCVD process. The thinnest SiO<sub>2</sub> on the s-Ge is achieved by low temperature remote plasma oxidation of a thin Si cap. As a result, 3X drive current enhancement is demonstrated on the fabricated s-Ge channel PMOSFETs over the Si controls. In addition, an appropriate threshold voltage (Vth) is demonstrated on the HfO<sub>2</sub>/P+ poly Si gate PMOSFETs when using an s-Ge channel.
Electron Devices Meeting, 2004. IEDM Technical Digest. IEEE International; 01/2005
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E.P. Gusev,
C. Cabral Jr,
B.P. Under,
Y.H. Kim,
K. Maitra,
E. Carrier,
H. Nayfeh,
R. Amos,
G. Biery,
N. Bojarczuk, [......],
H. Ng,
P. Nguyen,
J. Newbury,
V. Paruchuri,
R. Rengarajan,
G. Shahidi,
A. Steegen,
M. Steen,
S. Zafar,
Y. Zhang
[show abstract]
[hide abstract]
ABSTRACT: The key result in this work is that FUSI/HfSi<sub>x</sub>O<sub>y</sub> gate stacks offer both significant gate leakage reduction (due to high-κ) and drive current improvement at T<sub>inv</sub> ∼ 2 nm (due to: (i) elimination of poly depletion effect, ∼ 0.5 nm, and (ii) the high mobility of HfSi<sub>x</sub>O<sub>y</sub>). We also demonstrate that threshold voltage for both PFETs and NFETs can be adjusted from midgap to the values of Vt(PFET)∼ -0.4 V and Vt(NFET) ∼ + 0.3 V by poly-Si predoping by implantation (Al or As) and FUSI alloying. Significantly improved charge trapping (V<sub>t</sub> stability) was found in the case of NiSi/ HfSi<sub>x</sub>O<sub>y</sub> compared to the same gate electrode with HfO<sub>2</sub> dielectric.
Electron Devices Meeting, 2004. IEDM Technical Digest. IEEE International; 01/2005
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[show abstract]
[hide abstract]
ABSTRACT: We report medium energy ion scattering results that determine the extent of Hf incorporation in the interfacial region of HfO2∕Si(001) films. The lack of change in the Hf backscatter peak after interlayer growth by in situ oxidation indicates extremely low levels of Hf incorporation. We conclude that silicate formation is not a significant factor in determining capacitances of HfO2∕Si(001) structures, provided that the deposition technique does not involve creation of a silicide as an intermediate step.
Applied Physics Letters 07/2004; 85(3):458-460. · 3.84 Impact Factor
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E. Cartier,
V. Narayanan,
E.P. Gusev, P. Jamison,
B. Linder,
M. Steen,
K.K. Chan,
M. Frank,
N. Bojarczuk,
M. Copel, [......],
A. Callegari,
M. Gribelyuk,
M.P. Chudzik,
C. Cabral Jr,
R. Carruthers,
C. D'Emic,
J. Newbury,
D. Lacey,
S. Guha,
R. Jammy
[show abstract]
[hide abstract]
ABSTRACT: The flatband/threshold voltages (V<sub>fb</sub>/V<sub>t</sub>) in poly-Si gated pFETs with Hf-based gate dielectrics are shown to be set during poly-Si deposition and are found to remain virtually unchanged during gate implantation and activation, independent of the p-type dopant. The reaction of Si with HfO<sub>2</sub> at poly-Si deposition temperatures is identified as the root cause for the poor V<sub>fb</sub>/V<sub>t</sub> control. No improvement in V<sub>t</sub> control is obtained by engineering physically closed Si<sub>3</sub>N<sub>4</sub> barrier layers on HfO<sub>2</sub>. It is furthermore shown for the first time that even when the gate is fully silicided (FUSI) large V<sub>fb</sub>/V<sub>t</sub> shifts are observed with HfO<sub>2</sub>. Reduced pFET shifts are observed when Hf-silicates with low Hf content are used and further improvements are observed by using Al<sub>2</sub>O<sub>3</sub> cap layers on silicates.
VLSI Technology, 2004. Digest of Technical Papers. 2004 Symposium on; 07/2004
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D.-G. Park,
Z.J. Luo,
N. Edleman,
W. Zhu,
P. Nguyen,
K. Wong,
C. Cabral, P. Jamison,
B.H. Lee,
A. Chou, [......],
P. Kozlowski,
C. D'Emic,
V. Narayanan,
A. Steegen,
R. Wise,
R. Jammy,
R. Rengarajan,
H. Ng,
A. Sekiguchi,
C.H. Wann
[show abstract]
[hide abstract]
ABSTRACT: Thermally stable dual work function metal gates are demonstrated using a conventional CMOS process flow. The gate structure consists of poly-Si/metal nitrides (MN<sub>x</sub>) SiON (or high-k)/Si stack with atomic layer deposition (ALD)-TaN<sub>x</sub> for the NFET and ALD-WN<sub>x</sub> for the PFET. Much enhanced drive current (I<sub>d</sub>) and transconductance (G<sub>m</sub>) values, and reduced off current (I<sub>off</sub>) characteristics were attained with ALD-MN<sub>x</sub> gated devices over control poly-Si and PVD-MN<sub>x</sub> devices within controllable V<sub>t</sub> shifts. Excellent scalability of dual work function MN<sub>x</sub>/high-k gate stack was demonstrated: the EOT was down to 6.6Å with low leakage in a low thermal budget device scheme.
VLSI Technology, 2004. Digest of Technical Papers. 2004 Symposium on; 07/2004
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V. Narayanan,
A. Callegari,
F.R. McFeely,
K. Nakamura, P. Jamison,
S. Zafar,
E. Cartier,
A. Steegen,
V. Ku,
P. Nguyen, [......],
Y. Kawano,
D. Lacey,
Y. Li,
E. Sikorski,
F. Duch,
H. Ng,
C. Wann,
R. Jammy,
M. Ieong,
G. Shahidi
[show abstract]
[hide abstract]
ABSTRACT: Dual workfunction metal gated MOSFETs with CVD TaSiN, W and Re have been fabricated on HfO<sub>2</sub>. T<sub>inv</sub> as low as 1.46 nm with appropriate Vts and sub-threshold slopes 90 mV/decade or better have been achieved. For the first time we report low damage CVD processes for achieving dual workfunction metal gates in contrast to most reports in literature. Excellent hole mobility has been obtained for aggressive stacks. It is further observed that electron mobility optimization is critically dependent on specific electrode and interface layer combinations along with post deposition processing even for nominally identical HfO<sub>2</sub> layers.
VLSI Technology, 2004. Digest of Technical Papers. 2004 Symposium on; 07/2004
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B. Doris,
M. Ieong,
T. Zhu,
Y. Zhang,
M. Steen,
W. Natzle,
S. Callegari,
V. Narayanan,
J. Cai,
S.H. Ku, [......],
V. Ku,
T. Boyd,
T. Kanarsky,
C. D'Emic,
M. Newport,
D. Dobuzinsky,
S. Deshpande,
J. Petrus,
R. Jammy,
W. Haensch
[show abstract]
[hide abstract]
ABSTRACT: The ultra-thin SOI (UTSOI) device is an attractive choice for sub-10 nm gate-length scaling. In this work the major issues for UTSOI are addressed. External resistance is minimized by using the raised extension (REX) process flow which features an offset spacer to minimize the region of UTSOI outside the channel. The REX process scheme is used to demonstrate improved pFET performance and also to demonstrate the first planar single gate nFET with 8 nm gate-length. High temperature mobility measurements show that the channel thickness can be scaled further than previously predicted. UTSOI devices with tungsten gates and HfO<sub>2</sub> gate dielectrics having appropriate threshold voltages are presented for the first time.
Electron Devices Meeting, 2003. IEDM '03 Technical Digest. IEEE International; 01/2004
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[show abstract]
[hide abstract]
ABSTRACT: The thermal stability of polycrystalline silicon (poly-Si)/ZrO2 interface was significantly enhanced when the poly-Si was plasma deposited using silane heavily diluted in He. With regard to this process, transmission electron microscopy shows a sharp poly-Si/ZrO2 interface that is stable at 1000 °C. When the poly-Si was deposited by chemical vapor deposition using undiluted silane gas, transmission electron microscopy shows strong reactions at the poly-Si/ZrO2 interface when annealed at 1000 °C. The increased stability can be attributed to He dilution, which may prevent hydrogen from reducing the metal oxide. Another explanation may be directly related to He-excited plasma, which is known to produce denser and more stable films. © 2002 American Institute of Physics.
Applied Physics Letters 11/2002; 81(22):4157-4158. · 3.84 Impact Factor
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J.W. Sleight,
P.R. Varekamp,
N. Lustig,
J. Adkisson,
A. Allen,
O. Bula,
X. Chen,
T. Chou,
W. Chu,
J. Fitzsimmons, [......],
S. Womack,
E. Barth,
G. Biery,
C. Davis,
R. Ferguson,
R. Goldblatt,
E. Leobandung,
J. Weiser,
I. Yang,
P. Agnello
[show abstract]
[hide abstract]
ABSTRACT: This paper describes a second generation 1.2 V high performance
0.13 μm SOI technology. Aggressive ground rules and a tungsten
damascene local interconnect render the densest 6T 0.13 μm SRAM
reported to date with a cell area of 1.80 μm<sup>2</sup>. 248 nm
lithography is used for all critical levels. Interconnect performance
requirements are achieved by using up to 8 levels of Cu wiring and an
advanced BEOL process with low-k interlevel dielectrics and SiC barrier
layers
Electron Devices Meeting, 2001. IEDM Technical Digest. International; 02/2001
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K.L. Lee,
M.M. Frank,
V. Paruchuri,
E. Cartier,
B. Linder,
N. Bojarczuk,
X. Wang,
J. Rubino,
M. Steen,
P. Kozlowski, [......],
P. Flaitz,
M. Gribelyuk, P. Jamison,
G. Singco,
V. Narayanan,
S. Zafar,
S. Guha,
P. Oldiges,
R. Jammy,
M. Ieong
[show abstract]
[hide abstract]
ABSTRACT: A scalable poly-Si/AlN/HfSiO gate stack, implementing a new aluminum nitride (AlN) cap layer, combined with oxygen diffusion barrier, halo and counter doping engineering, high temperature spike anneal for gate and junction activation, and optional inverted gate implant, has been successfully developed to fully offset the large threshold voltage (V<sub>t</sub>) shifts in poly-Si/HfSiO devices and achieve good thickness scalability and gate stack stability. The new AlN cap layers provide better PFET V<sub>t</sub> control than, for example, Al<sub>2</sub>O<sub>3</sub> layers, and can be removed from NFETs without impacting device properties. We thus have achieved sub-100 nm device V<sub>t</sub> of 0.3-0.4 V with PFETs I<sub>on</sub> ~ 140 muA/mum at I<sub>off</sub> ~13 pA/mum, suitable for low-power technologies. Carrier mobilities are close to those of SiON control devices. Thus the V<sub>t</sub> problem impeding the implementation of poly-Si/high-k gate stacks for low power device applications has been resolved
VLSI Technology, 2006. Digest of Technical Papers. 2006 Symposium on;
