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ABSTRACT: Factors responsible for the undesirably high values of positive-channel (p-channel) threshold voltage (Vt) in high-κ metal oxide semiconductor transistors are investigated. In silicon/silicon dioxide/hafnium dioxide/metal gate transistors an anomalous nonlinear relationship between the equivalent oxide thickness (EOT) and Vt occurs when the silicon dioxide (SiO2) interface layer is sufficiently thin (<2.3 nm). The deviation from the expected EOT versus Vt behavior is shown to be related to processing temperature, metal work-function, substrate doping type, and thickness of the high-κ material. This result, coupled with charge trapping measurements on samples with different SiO2 interface layer thickness, suggests that the loss of negative fixed charge via the tunneling of trapped electrons to the substrate is a possible explanation for the elevated p-channel Vt.
Journal of Applied Physics 10/2007; 102(7):074511-074511-5. · 2.17 Impact Factor
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ABSTRACT: We report on the development of a hafnium zirconate (HfZrO4) alloy gate dielectric for advanced gate stack applications. The HfZrO4 and hafnium dioxide (HfO2) films were formed by atomic layer deposition using metal halides and heavy water as precursors. The HfZrO4 material properties were examined and compared with those of HfO2 by a wide variety of analytical methods. The dielectric properties, device performance, and reliability of HfZrO4 were investigated by fabricating HfZrO4/tantalum carbide (TaxCy) metal-oxide-semiconductor field effect transistor. The HfZrO4 dielectric film has smaller band gap, smaller and more uniform grains, less charge traps, and more uniform film quality than HfO2. The HfZrO4 dielectric films exhibited good thermal stability with silicon. Compared to HfO2, the HfZrO4 gate dielectric showed lower capacitance equivalent thickness value, higher transconductance, less charge trapping, higher drive current, lower threshold voltage (Vt), reduced capacitance-voltage (C-V) hysteresis, lower interface state density, superior wafer level thickness uniformity, and longer positive bias temperature instability lifetime. Incorporation of zirconium dioxide (ZrO2) into HfO2 enhances the dielectric constant (k) of the resulting HfZrO4 which is associated with structural phase transformation from mainly monoclinic to tetragonal. The tetragonal phase increases the k value of HfZrO4 dielectric to a large value as predicted. The improved device characteristics are attributed to less oxygen vacancy in the fine grained microstructure of HfZrO4 films.
Journal of Applied Physics 04/2007; 101(7):074113-074113-7. · 2.17 Impact Factor
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A. V-Y Thean,
Z-H Shi,
L. Mathew,
T. Stephens,
H. Desjardin,
C. Parker,
T. White,
M. Stoker,
L. Prabhu,
R. Garcia,
B-Y. Nguyen,
S. Murphy,
R. Rai,
J. Conner, B. E. White,
S. Venkatesan
[show abstract]
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ABSTRACT: This paper compares the performance and inter-die variability of doped and undoped channel multiple-gate FETs (MUGFETs) with respect to planar SOI devices. We show that doped-channel FinFETs have equivalent variability to narrow-width planar devices. As such, transitions to FinFETs for narrow-width devices will likely incur minimal variability impact. To match the low variability of wide-width planar devices, conversions to undoped channel FinFETs is necessary. Furthermore, good short-channel control has to be maintained since undoped channel devices exhibit increase sensitivity to Tbody relative to doped channel FinFETs due to enhanced fully-depleted channel electrostatics
Electron Devices Meeting, 2006. IEDM '06. International; 01/2007
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J. K. Schaeffer,
C. Capasso,
R. Gregory,
D. Gilmer,
L. R. C. Fonseca,
M. Raymond,
C. Happ,
M. Kottke,
S. B. Samavedam,
P. J. Tobin, B. E. White
[show abstract]
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ABSTRACT: The intent of this research is to understand the role of interface chemistry on the effective work function and device characteristics of metal gate electrodes on hafnium dioxide (HfO2) gate dielectrics in metal oxide semiconductor field effect transistors. Since multiple factors, including crystal structure, preferred orientation, chemical composition, interface bonding, and reactions or interdiffusions, impact the effective work function, solid-solution carbonitrides of tantalum (TaCxN1−x) have been studied in an attempt to isolate the role of interface chemistry on the effective work function. Tantalum carbonitride films have been carefully deposited with similar Ta/(C+N) ratios to understand how the substitution of N for C on the octahedral interstice in a face-centered-cubic tantalum lattice impacts device performance. Results indicate that the effective work function and device threshold voltage are reduced when the less electronegative carbon atom is substituted for the more electronegative nitrogen atom. This result is in qualitative agreement with the known relationship between metal electronegativity and effective work function and demonstrates the important role that sublattice elements in binary metal compounds have on the effective work function of the gate electrode.
Journal of Applied Physics. 01/2007; 101(1):014503-014503-9.
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ABSTRACT: Atomic layer deposited HfO2 films void and exhibit poor electrical characteristics when annealed at high temperature unless a TiN capping layer is used. The TiN is removed prior to characterization of the dielectric. The authors find that capped HfO2 films annealed at 1000 °C by rapid thermal process are smooth and void-free. The microstructure of HfO2 is modified from fully monoclinic to a mixed monoclinic and tetragonal phase when the capping layer is used. Conducting atomic force microscopy performed on these films shows fewer areas with high leakage current. Mo/HfO2 capacitors show improved CV characteristics and lower leakage current density.
Applied Physics Letters 09/2006; 89(13):132903-132903-3. · 3.84 Impact Factor
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[show abstract]
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ABSTRACT: Thin film characteristics of
mixed oxides and nanolaminates formed by atomic layer deposition were studied using transmission electron microscopy (TEM),
atomic force microscopy, X-ray reflectometry, and metal oxide semiconductor capacitors. The role of
underlayer and the impact of the location of
in
gate dielectrics were also investigated. Some differences in grain-size distribution were observed between mixed oxides and
nanolaminates. In mixed oxide films, the grains became smaller and clustered together to form elongated structures as
is added. For nanolaminates, the grains became smaller than
but they did not form elongated structures. Cross-sectional TEM showed that as-deposited
films were amorphous with a thinner interfacial layer than that of
. After annealing, films became rougher, with an increase in interfacial layer thickness. A minimum of
of
was needed as an underlayer to obtain well-behaved electrical characteristics. Capacitance-voltage stressing performed on
these films showed improved charge trapping behavior for mixed oxide and nanolaminate structures.
Journal of The Electrochemical Society. 08/2006; 153(9):G834-G839.
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ABSTRACT: The impact of Zr addition on microstructure of HfO2 after high temperature processing was investigated using Rutherford backscattering, x-ray diffraction (XRD), transmission electron microscopy, and atomic force microscopy (AFM). The ZrO2 content in the films was varied from ∼ 25% to 75%. XRD analysis shows that adding >50% ZrO2 leads to partial stabilization of tetragonal phase of the HfxZr1−xO2 alloy. AFM images revealed smaller grains with Zr addition. Conducting AFM showed more uniform and tighter tunneling current distribution in HfxZr1−xO2 compared to HfO2. Constant capacitance-voltage stressing performed on HfO2 and HfxZr1−xO2 metal-oxide-semiconductor capacitors indicated reduced charge trapping with Zr addition.
Applied Physics Letters 05/2006; 88(22):222901-222901-3. · 3.84 Impact Factor
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H.-H. Tseng,
P.J. Tobin,
E.A. Hebert,
S. Kalpat,
M.E. Ramon,
L. Fonseca,
Z.X. Jiang,
J.K. Schaeffer,
R.I. Hegde,
D.H. Triyoso, [......],
D. Sing,
J. Conner,
E. Luckowski,
B.W. Chan,
A. Haggag,
S. Backer,
R. Noble,
M. Jahanbani,
Y.H. Chili, B.E. White
[show abstract]
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ABSTRACT: Using a novel fluorinated Ta<sub>x</sub>C<sub>y</sub>/high-k gate stack, we show breakthrough device reliability and performance improvements. This is a critical result since threshold voltage instability may be a fundamental problem and performance degradation for high-k is a concern. The novel fluorinated gate stack device exceeds the PBTI and NBTI targets with sufficient margin and has electron mobility comparable to the best polySi/SiON device on bulk Si reported so far
Electron Devices Meeting, 2005. IEDM Technical Digest. IEEE International; 01/2006
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D. H. Triyoso,
R. I. Hegde,
S. Zollner,
M. E. Ramon,
S. Kalpat,
R. Gregory,
X.-D. Wang,
J. Jiang,
M. Raymond,
R. Rai,
D. Werho,
D. Roan, B. E. White,
P. J. Tobin
[show abstract]
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ABSTRACT: The impact of 8-to 45-at. % Ti on physical and electrical characteristics of atomic-layer-deposited and annealed hafnium dioxide was studied using vacuum-ultraviolet spectroscopic ellipsometry, secondary ion mass spectroscopy, transmission electron microscopy, atomic force microscopy, x-ray diffraction, Rutherford backscattering spectroscopy, x-ray photoelectron spectroscopy, and x-ray reflectometry. The role of Ti addition on the electrical performance is investigated using molybdenum (Mo)-gated capacitors. The film density decreases with increasing Ti addition. Ti addition stabilizes the amorphous phase of HfO2, resulting in amorphous films as deposited. After a high-temperature annealing, the films transition from an amorphous to a polycrystalline phase. Orthorhombic Hf–Ti–O peaks are detected in polycrystalline films containing 33-at. % or higher Ti content. As Ti content is decreased, monoclinic HfO2 becomes the predominant microstructure. No TiSi is formed at the dielectric/Si interface, indicating films with good thermal stability. The band gap of Hf–Ti–O was found to be lower than that of HfO2. Well-behaved capacitance-voltage and leakage current density-voltage characteristics were obtained for Hf–Ti–O. However, an increased leakage current density was observed with Ti addition. The data from capacitance-voltage stressing indicate a smaller flatband voltage (Vfb) shift in the HfO2 films with low Ti content when compared with the HfO2 films. This indicates less charge trapping with a small amount of Ti addition.
Journal of Applied Physics 09/2005; 98(5):054104-054104-8. · 2.17 Impact Factor
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H.-H. Tseng,
J.M. Grant,
C. Hobbs,
P.J. Tobin,
L. Hebert,
M. Ramon,
S. Kalpat,
F. Wang,
D. Triyoso,
D.C. Gilmer, B.E. White,
P. Abramowitz,
M. Moosa,
Z. Luo,
T.P. Ma
[show abstract]
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ABSTRACT: To achieve a lower gate leakage in high speed devices at the same equivalent oxide thickness, a major thrust is to replace the SiO<sub>2</sub> with a thicker dielectric that has a higher dielectric constant. Recently, there has been much interest in hafnium dioxide as a potential high-k gate dielectric as presented in E. P Gusev et a. (2001), B. Barlage et al. (2001), G. Wilk et al. (2001), C. Hobbs et al. (2001), W. Zhu et al. (2001), W. Qi et al. (2000) and B. Lee et al. (1999) due to its high permittivity. However, the polycrystalline microstructure may be undesirable. In order to increase the crystallization temperature, SiO<sub>2</sub> or Al<sub>2</sub>O<sub>3</sub> are added to HfO<sub>2</sub> to form Hf silicates atid Hf aluminates. A systematic study to compare the device characteristics of these three major candidates is needed. In this work, we have compared them in terms of the key challenges of high-K devices such as Gm degradation, Vt instability, and reliability, in devices fabricated with a conventional CMOS process technology according to A. Perera et al. (2000).
VLSI Technology, 2005. (VLSI-TSA-Tech). 2005 IEEE VLSI-TSA International Symposium on; 05/2005
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ABSTRACT: In this article, we evaluated physical and electrical characteristics of La-based gate dielectrics ( La <sub>2</sub> O <sub>3</sub> and La Al <sub>x</sub> O <sub>y</sub> ) deposited by atomic layer deposition (ALD). The precursors used for La <sub>2</sub> O <sub>3</sub> and La Al <sub>x</sub> O <sub>y</sub> are lanthanum tris[bis(trimethylsilyl)amide] La [ N ( Si Me <sub>3</sub>)<sub>2</sub>]<sub>3</sub> , trimethyl aluminum [ Al ( CH <sub>3</sub>)<sub>3</sub>] , and water. Physical properties of these dielectric films were studied using ellipsometry, x-ray photoelectron spectroscopy (XPS), and transmission electron microscopy (TEM). To investigate electrical properties of these La-based dielectrics, metal oxide semiconductor capacitors (MOSCAPs) were fabricated using metal gates (Ta–Si–N, TiN and Pt). Linear growth rate characteristics were observed for ALD ( La <sub>2</sub> O <sub>3</sub> and La Al <sub>x</sub> O <sub>y</sub> films deposited at temperatures of 225 to 275 ° C . XPS and XTEM analysis of La-based films grown on a chemical oxide starting surface revealed a rough La-based dielectric/Si interface and chemical interaction with the Si substrate. In general, adding Al into La <sub>2</sub> O <sub>3</sub> improved electrical properties of the films. Devices with La based dielectric deposited on a ∼10 Å Al <sub>2</sub><rom-
-
an>O <sub>3</sub> underlayer had better capacitance-voltage characteristics compared to those deposited directly on a chemical oxide surface. Adding Al to the dielectric also resulted in lower leakage current and smaller hysteresis. For devices with Ta–Si–N gates, a significant decrease in maximum capacitances was observed after forming gas annealing, probably due to interaction between the gate electrode and the dielectric. XTEM images for these devices indicated an indistinct interface between the Ta–Si–N gate and the La-based dielectrics. The XTEM images also showed microcrystals in Ta–Si–N that may be formed in Si deficient regions of the metal gate. No interaction between TiN or Pt with La gate dielectrics was observed by XTEM up to 800 ° C annealing temperature. After 900 ° C annealing, some interaction between La Al <sub>x</sub> O <sub>y</sub> and Pt gate was observed. Our results indicated that silicon substrate interactions may limit the utilization of ALD La based dielectrics in future complementary metal-oxide semiconductor processing.
Journal of vacuum science & technology. B, Microelectronics and nanometer structures: processing, measurement, and phenomena: an official journal of the American Vacuum Society 02/2005; · 1.34 Impact Factor
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H.-H. Tseng,
C.C. Capasso,
J.K. Schaeffer,
E.A. Hebert,
P.J. Tobin,
D.C. Gilmer,
D. Triyoso,
M.E. Ramon,
S. Kalpat,
E. Luckowski,
W.J. Taylor,
Y. Jeon,
O. Adetutu,
R.I. Hegde,
R. Noble,
M. Jahanbani,
C. El Chemali, B.E. White
[show abstract]
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ABSTRACT: Threshold voltage instability is a critical problem for high-K dielectric implementation. This problem is much more serious for short channel devices due to process induced gate edge damage. A novel stress relieved pre-oxide (SRPO) followed by ALD of HfO<sub>2</sub> reduces the local charge density near the gate edge and short channel threshold voltage instability. Excellent cross wafer CETinv uniformity is achieved for the SRPO process. A new tantalum carbon alloy metal gate achieves a lower Vtsat than TaSiN gated devices due to a lower work function. Compared to HfO<sub>2</sub>/TaSiN devices using standard RCA pre-clean, HfO<sub>2</sub>/tantalum carbon alloy metal gate stack using the novel SRPO demonstrates a 3× smaller Vt shift for short channel devices and a 16% Ion/Ioff improvement.
Electron Devices Meeting, 2004. IEDM Technical Digest. IEEE International; 01/2005
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L. Mathew,
Y. Du,
A.V.-Y. Thean,
M. Sadd,
A. Vandooren,
C. Parker,
T. Stephens,
R. Mora,
R. Rai,
M. Zavala, [......],
S. Kalpat,
J. Hughes,
R. Shimer,
S. Jallepalli,
G. Workman,
W. Zhang,
J.G. Fossum, B.E. White,
B.-Y. Nguyen,
J. Mogab
[show abstract]
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ABSTRACT: Perfectly self aligned vertical multiple independent gate field effect transistor (MIGFET) CMOS devices have been fabricated. The unique process used to fabricate these devices allow them to be integrated with FinFET devices. Device and circuit simulations have been used to explain the device and explore new applications using this device. A novel application of the MIGFET as a signal mixer has been demonstrated. The undoped channel, very thin body, perfectly matched gates allows charge coupling of the two signals and provide a new family of applications using the MIGFET mixer. Since the process allows integration of regular CMOS double gate devices and MIGFET devices this technology has potential for various digital and analog mixed-signal applications.
SOI Conference, 2004. Proceedings. 2004 IEEE International; 11/2004
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ABSTRACT: The intrinsic and extrinsic contributions to Fermi level pinning of platinum ( Pt ) electrodes on hafnium dioxide ( HfO <sub>2</sub>) gate dielectrics are investigated by examining the impact of oxygen and forming gas anneals on the effective work function of Pt - HfO <sub>2</sub> -silicon capacitors. The effective platinum work function is ∼4.6 eV when annealed in forming gas. However, diffusion of oxygen to the Pt / HfO <sub>2</sub> interface increases the platinum work function to a value of ∼4.9 eV . Subsequent annealing in forming gas returns the platinum work function to a value comparable to that measured prior to the oxygen anneal. The effective platinum work functions are compared to the prediction of the metal induced gap states (MIGS) model. The presence of interfacial oxygen vacancies or platinum–hafnium bonds is believed to be responsible for a degree of pinning that is stronger than predicted from the MIGS model alone.
Applied Physics Letters 10/2004; · 3.84 Impact Factor
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A.V.-Y. Thean,
A. Vandooren,
S. Kalpat,
Y. Du,
I. To,
J. Hughes,
T. Stephens,
B. Goolsby,
T. White,
A. Barr, [......],
M. Rossow,
D. Roan,
D. Pham,
R. Rai,
S. Murphy,
B.-Y. Nguyen, B.E. White,
A. Duvallet,
T. Dao,
J. Mogab
[show abstract]
[hide abstract]
ABSTRACT: In this paper, we report the performance and reliability of sub-100nm TaSiN metal gate fully depleted SOI devices with high-k gate dielectric. Performance differences between fully-depleted and partially-depleted devices are highlighted. This is also the first time that an unique asymmetric degradation phenomenon between electron and hole mobility in metal/high-k devices is reported. Despite the use of high-k dielectric, we show that these devices exhibit superior reliability, noise and analog circuit performances.
VLSI Technology, 2004. Digest of Technical Papers. 2004 Symposium on; 07/2004
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C.C. Hobbs,
L.R.C. Fonseca,
A. Knizhnik,
V. Dhandapani,
S.B. Samavedam,
W.J. Taylor,
J.M. Grant,
L.G. Dip,
D.H. Triyoso,
R.I. Hegde,
D.C. Gilmer,
R. Garcia,
D. Roan,
M.L. Lovejoy,
R.S. Rai,
E.A. Hebert,
Hsing-Huang Tseng,
S.G.H. Anderson, B.E. White,
P.J. Tobin
[show abstract]
[hide abstract]
ABSTRACT: We report here that Fermi pinning at the polysilicon/metal-oxide interface causes high threshold voltages in MOSFET devices. In Part I, we investigated the different gatestack regions and determined that the polysilicon/metal oxide interface plays a key role on the threshold voltages. Now in Part II, the effects of the interfacial bonding are examined by experiments with submonolayer atomic-layer deposition (ALD) metal oxides and atomistic simulation. Results indicate that pinning occurs due to the interfacial Si-Hf and Si-O-Al bonds for HfO<sub>2</sub> and Al<sub>2</sub>O<sub>3</sub>, respectively. Oxygen vacancies at polysilicon/HfO<sub>2</sub> interfaces also lead to Fermi pinning. This fundamental characteristic affects the observed polysilicon depletion.
IEEE Transactions on Electron Devices 07/2004; · 2.32 Impact Factor
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C.C. Hobbs,
L.R.C. Fonseca,
A. Knizhnik,
V. Dhandapani,
S.B. Samavedam,
W.J. Taylor,
J.M. Grant,
L.G. Dip,
D.H. Triyoso,
R.I. Hegde,
D.C. Gilmer,
R. Garcia,
D. Roan,
M.L. Lovejoy,
R.S. Rai,
E.A. Hebert,
Hsing-Huang Tseng,
S.G.H. Anderson, B.E. White,
P.J. Tobin
[show abstract]
[hide abstract]
ABSTRACT: We report here that Fermi pinning at the polysilicon/metal oxide interface causes high threshold voltages in MOSFET devices. Results indicate that pinning occurs due to the interfacial Si-Hf and Si-O-Al bonds for HfO<sub>2</sub> and Al<sub>2</sub>O<sub>3</sub>, respectively. Oxygen vacancies at polysilicon/HfO<sub>2</sub> interfaces also lead to Fermi pinning. We show that this fundamental characteristic affects the observed polysilicon depletion. In Part I, the theoretical background is reviewed and the impact of the different gate stack regions are separated out by investigating the relative threshold voltage shifts of devices with Hf-based dielectrics. The effects of the interfacial bonding are examined in Part II.
IEEE Transactions on Electron Devices 07/2004; · 2.32 Impact Factor
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L. Mathew,
Yang Du,
A.V.-Y. Thean,
M. Sadd,
A. Vandooren,
C. Parker,
T. Stephens,
R. Mora,
Raghav Rai,
M. Zavala,
D. Sing,
S. Kalpai,
J. Hughes,
R. Shimer,
S. Jallepalli,
G. Workman, B.E. White,
B.-Y. Nguyen,
A. Mogab
[show abstract]
[hide abstract]
ABSTRACT: Device architectures incorporating multiple gate structures have been proposed to allow transistor scaling beyond the planar MCSFET integrations. These device architectures can improve performance such as better short channel performance and reduced leakage. In addition the additional channel surface and gate electrodes offers new circuit possibilities such as dynamic threshold voltage control and an RF mixer are demonstrated. It is desirable to fabricate multi-gated devices with the single gate on multiple sides and multiple gate electrodes this has been demonstrated successfully.
Integrated Circuit Design and Technology, 2004. ICICDT '04. International Conference on; 02/2004
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H.-H. Tseng,
M.E. Ramon,
L. Hebert,
P.J. Tobin,
D. Triyoso,
S. Kalpat,
J.M. Grant,
Z.X. Jiang,
D.C. Gilmer,
D. Menke,
W.J. Taylor,
O. Adetutu, B.E. White
[show abstract]
[hide abstract]
ABSTRACT: Device instability is one of the most challenging issues to implement High-K gate dielectric. Incorporation of deuterium during the ALD process effectively improves the interface quality that enhances High-K device stability and reliability. Compared to H<sub>2</sub>O processed HfO<sub>2</sub> devices, devices with D<sub>2</sub>O processing result in a significantly smaller Vt shift after constant voltage stressing at room temperature and at 125°C under NBTI/PBTI conditions, as well as a longer CHCI lifetime. This process is independent of transistor process integration and is relatively low cost. It has the potential to become an industry standard if ALD High-K gate dielectric processing is the final choice.
Integrated Circuit Design and Technology, 2004. ICICDT '04. International Conference on; 02/2004
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H.-H. Tseng,
M.E. Ramon,
L. Hebert,
P.J. Tobin,
D. Triyoso,
J.M. Grant,
Z.X. Jiang,
D. Roan,
S.B. Samavedam,
D.C. Gilmer,
S. Kalpat,
C. Hobbs,
W.J. Taylor,
O. Adetutu, B.E. White
[show abstract]
[hide abstract]
ABSTRACT: Device instability is one of the most challenging issues to implement high-k gate dielectrics. Incorporation of deuterium during the ALD (atomic layer deposition) process effectively improves the interface quality that enhances high-k device stability and reliability. Compared to H<sub>2</sub>O processed HfO<sub>2</sub> devices, devices with D<sub>2</sub>O processing result in a significantly smaller Vt shift after constant voltage stressing at room temperature and at 125°C under NBTI/PBTI conditions, as well as a longer CHCI lifetime. This process is independent of transistor process integration and is relatively low cost. It has the potential to become an industry standard if ALD high-k gate dielectric processing is the final choice.
Electron Devices Meeting, 2003. IEDM '03 Technical Digest. IEEE International; 01/2004
