Jui-Jer Huang

National Taiwan University, Taipei, Taipei, Taiwan

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Publications (4)0.45 Total impact

  • Jui-Jer Huang, Chiuan-Che Li, Jiun-Lang Huang
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    ABSTRACT: This paper presents a low-cost wafer-level test methodology for the source driver ICs of liquid crystal displays; the idea is to realize the test circuitry on the wafer scribe line. The proposed technique not only substantially reduces the required ATE I/O channels but also eliminates the need of high-speed digitization units on the ATE. Furthermore, because the test circuitry is realized on the scribe line, no modification is made to the circuit under test, i.e., the proposed methodology does not incur any area or performance overhead.
    Proceedings of the Asian Test Symposium 01/2008;
  • [show abstract] [hide abstract]
    ABSTRACT: In this paper, we present a BIST technique that measures the RMS value of a Gaussian distribution period jitter. In the proposed approach, the signal under test is delayed by two different delay values and the probabilities it leads the two delayed signals are measured. The RMS jitter can then be derived from the probabilities and the delay values. Behavior and circuit simulations are performed to validate the proposed technique and analyze the design tradeoffs, and preliminary measurement results on FPGA are also presented.
    Journal of Electronic Testing 05/2006; 22(3):219-228. · 0.45 Impact Factor
  • Source
    Jui-Jer Huang, Jiun-Lang Huang
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    ABSTRACT: In this paper, we present an infrastructure IP core to facilitate on-chip clock jitter measurement. In the proposed approach, the clock signal under test is delayed by two different delay values and the probabilities it leads the two delayed versions are measured. The RMS period jitter value can then be derived from the probabilities and the delay difference. Both behavior and circuit simulations are performed to validate the proposed technique and analyze the design tradeoffs, and a prototype chip has been designed for further validation.
    Computer Design: VLSI in Computers and Processors, 2004. ICCD 2004. Proceedings. IEEE International Conference on; 11/2004
  • Source
    Jui-Jer Huang, Jiun-Lang Huang
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    ABSTRACT: In this paper, we present a technique to measure the RMS period jitter of the signal under test. In the proposed approach, the lead/lag relationships between the signal under test and two delayed versions of itself are compared. The collected information corresponds to two points along the jitter's cumulative distribution function (CDF) curve from which the RMS period jitter value can be derived. Currently, SPICE simulation results show less than 5% error for RMS jitter values ranging from 40 to 60 ps.
    Test Symposium, 2003. ATS 2003. 12th Asian; 12/2003

Publication Stats

18 Citations
1 Download
226 Views
0.45 Total Impact Points

Institutions

  • 2003
    • National Taiwan University
      • Department of Electrical Engineering
      Taipei, Taipei, Taiwan