Shao-Ming Yu

National Chiao Tung University, Hsin-chu-hsien, Taiwan, Taiwan

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Publications (40)32.02 Total impact

  • [Show abstract] [Hide abstract]
    ABSTRACT: FinFET is the most promising double-gate transistor architecture to extend scaling over planar device. We present a high-performance and low-power FinFET module at 25 nm gate length. When normalized to the actual fin perimeter, N-FinFET and P-FinFET have 1200 and 915 ¿A/¿m drive current respectively at 100 nA/¿m leakage under 1V. To our knowledge this is the best FinFET drive current at such scaled gate length. This scaled gate length enables this FinFET transistor for 32 nm node insertion. With aggressive fin pitch scaling, the effective transistor width is approximately 1.9X and 2.7X over planar for typical logic and SRAM on the same layout area (i.e., silicon real estate). Due to superior electrostatics and reduced random dopant fluctuation, this high drive current can be readily traded with V<sub>DD</sub> scaling for low power.
    Electron Devices Meeting (IEDM), 2009 IEEE International; 01/2010
  • Article: Preface
    Mathematical and Computer Modelling 01/2010; 51(1-2):855-856. DOI:10.1016/j.mcm.2013.04.004 · 2.02 Impact Factor
  • Yiming Li · Shao-Ming Yu · Yih-Lang Li
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    ABSTRACT: Optical lithography is one of the key technologies in semiconductor material and device fabrications. It is a process to transfer the layouts of desired pattern onto the wafers. However, the exposure on wafer has distortions due to the proximity effects. As the minimum feature sizes of explored samples continue to shrink, the mismatch between the pattern and the experimental result on wafer is significant. Corrections of mask patterns between the sample and post exposure result are thus necessary. Optical proximity correction (OPC) is the process of modifying the geometries of the layouts to compensate for the non-ideal properties of the lithography process. Given the shapes desired on the wafer, the mask is modified to improve the reproduction of the critical geometry. In this work, we propose an intelligent OPC technique for process distortion compensation of layout mask. To perform the mask correction in sub-wavelength era, two different strategies including the genetic algorithm (GA) with model-based OPC and the GA with rule-based OPC methods are examined. The proposed intelligent system consists of three parts: the pre-process, the OPC engine, and the post-process. During the pre-process, the pattern analyzer will analysis all patterns and then divided them into many segments for model-based OPC or generates assistant patterns for rule-based OPC. Secondly, the OPC module is applied to correct the mask. The intelligent module searches the whole problem domain to find out the best combination of the mask shape by the GA. The corrected mask is verified by performing lithographic simulation to get the error norm between exposed result and desired layout. Finally, the mask verification is conducted in the post-process. By testing on several fundamental patterns, this approach shows good correction accuracy and efficiency, compared with experimentally fabricated samples. It can be applied to perform the mask correction in sub-wavelength era.
    Computational Materials Science 03/2009; DOI:10.1016/j.commatsci.2008.04.031 · 2.13 Impact Factor
  • Yiming Li · Yih-Lang Li · Shao-Ming Yu
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    ABSTRACT: In this work, we implement a computational statistics technique for design optimization of integrated circuits (ICs). Integration of a well-known circuit simulation software and central composite design method enables us to construct a second-order response surface model (RSM) for each concerned constraint. After construction of RSMs, we verify the adequacy and accuracy using the normal residual plots and their residual of squares. The constructed models are further employed for design optimization of current mirror amplifier ICs with 0.18 m CMOS devices. By considering the voltage gain, cut-off frequency, phase margin, common-mode rejection ratio and slew-rate, six designing parameters including the width and length of different transistors are selected and optimized to fit the targets.
    Mathematics and Computers in Simulation 12/2008; DOI:10.1016/j.matcom.2007.11.002 · 0.86 Impact Factor
  • Source
    Yiming Li · Shao-Ming Yu · Yih-Lang Li
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    ABSTRACT: This work proposes an object-oriented unified optimization framework (UOF) for general problem optimization. Based on biological inspired techniques, numerical deterministic methods, and C++ objective design, the UOF itself has significant potential to perform optimization operations on various problems. The UOF provides basic interfaces to define a general problem and generic solver, enabling these two different research fields to be bridged. The components of the UOF can be separated into problem and solver components. These two parts work independently allowing high-level code to be reused, and rapidly adapted to new problems and solvers. The UOF is customized to deal with several optimization problems. The first experiment involves a well-known discrete combinational problem, wihle the second one studies the robustness for the reverse modeling problem, which is in high demanded by device manufacturing companies. Additionally, experiments are undertaken to determine the capability of the proposed methods in both analog and digital circuit design automation. The final experiment designs antenna for rapidly growing wireless communication. Most experiments are categorized as simulation-based optimization tasks in the microelectronics industry. The results confirm that UOF has excellent flexibility and extensibility to solve these problems successfully. The developed open-source project is publicly available.
    Mathematics and Computers in Simulation 12/2008; DOI:10.1016/j.matcom.2007.11.001 · 0.86 Impact Factor
  • Yiming Li · Shao-Ming Yu · Jiunn-Ren Hwang · Fu-Liang Yang
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    ABSTRACT: We experimentally quantified, for the first time, the random dopant distribution (RDD)-induced threshold voltage standard deviation up to 40 mV for 20-nm-gate planar complementary metal-oxide-semiconductor (CMOS) field-effect transistors. Discrete dopants have been statistically positioned in the 3-D channel region to examine the associated carrier transportation characteristics, concurrently capturing ldquodopant concentration variationrdquo and ldquodopant position fluctuation.rdquo As the gate length further scales down to 15 nm, the newly developed discrete dopant scheme features an effective solution to suppress the 3-sigma-edge single-digit dopant-induced variation by the gate work function modulation. The results of this paper may postpone the scaling limit projected for planar CMOS.
    IEEE Transactions on Electron Devices 07/2008; 55(6-55):1449 - 1455. DOI:10.1109/TED.2008.921991 · 2.36 Impact Factor
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    ABSTRACT: In this brief, shallow-trench-isolation (STI) stress buffer techniques, including sidewall stress buffer and channel surface buffer layers, are developed to reduce the impact of compressive STI stress on the mobility of advanced n-type MOS (NMOS) devices. Our investigation shows that a 7% driving current gain at an NMOS device has been achieved, whereas no degradation at a p-type MOS (PMOS) device was observed. The same junction leakage at both the NMOS and PMOS devices was maintained. A stress relaxation model with simulation is thus proposed to account for the enhanced transport characteristics.
    IEEE Transactions on Electron Devices 05/2008; 55(4-55):1085 - 1089. DOI:10.1109/TED.2008.916708 · 2.36 Impact Factor
  • Yiming Li · Shao-Ming Yu · Yih-Lang Li
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    ABSTRACT: It is known that a master equation characterizes time evolution of trajectories and transition of states in protein folding dynamics. Solution of the master equation may require calculating eigenvalues for the corresponding eigenvalue problem. In this paper, we numerically study the folding rate for a dynamic problem of protein folding by solving a large-scale eigenvalue problem. Three methods, the implicitly restarted Arnoldi, Jacobi–Davidson, and QR methods are employed in solving the corresponding large-scale eigenvalue problem for the transition matrix of master equation. Comparison shows that the QR method demands tremendous computing resource when the length of sequence L>10 due to extremely large size of matrix and CPU time limitation. The Jacobi–Davidson method may encounter convergence issue, for cases of L>9. The implicitly restarted Arnoldi method is suitable for solving problems among them. Parallelization of the implicitly restarted Arnoldi method is successfully implemented on a PC-based Linux cluster. The parallelization scheme mainly partitions the operation of matrix. For the Arnoldi factorization, we replicate the upper Hessenberg matrix Hm for each processor, and distribute the set of Arnoldi vectors Vm among processors. Each processor performs its own operation. The algorithm is implemented on a PC-based Linux cluster with message passing interface (MPI) libraries. Numerical experiment performing on our 32-nodes PC-based Linux cluster shows that the maximum difference among processors is within 10%. A 23-times speedup and 72% parallel efficiency are achieved when the matrix size is greater than 2×106 on the 32-nodes PC-based Linux cluster. This parallel approach enables us to explore large-scale dynamics of protein folding.
    Journal of Parallel and Distributed Computing 05/2008; DOI:10.1016/j.jpdc.2007.09.002 · 1.01 Impact Factor
  • Yiming Li · Shao-Ming Yu · Chih-Hong Hwang · Yi-Ting Kuo
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    ABSTRACT: In this study, a three-dimensional electro-thermal time-domain simulation is developed for dynamic thermal analysis of Phase change memories (PCMs). The geometry effects of the GeSbTe (GST) materials and the TiN heater are explored through a series of numerical examinations. It is found that the contact size of the GST significantly alters the maximum temperature of the PCMs, compared with the height of the GST films. The heater’s aspect ratio also dominates the maximum temperature of the GST material, and the effect of the heater’s thickness on the temperature is more evident than its height. One conformal bi-layer GST structure with different electric and thermal conductivities on the GST layers is examined for different applied currents to extract the curve of resistances versus applied currents.
    Journal of Computational Electronics 01/2008; 7(3):138-141. DOI:10.1007/s10825-008-0192-8 · 1.37 Impact Factor
  • Source
    Yiming Li · Shao-Ming Yu
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    ABSTRACT: In this paper, a simulation-based optimization methodology for nanoscale complementary metal-oxide-semiconductor (CMOS) device fabrication is advanced. Fluctuation of electrical characteristics is simultaneously considered and minimized in the optimization procedure. Integration of device and process simulation is implemented to evaluate device performances, where the hybrid intelligent approach enables us to extract optimal recipes which are subject to targeted device specification. Production of CMOS devices now enters the technology node of 65 nm; therefore, random-dopant-induced characteristic fluctuation should be minimized when a set of fabrication parameters is suggested. Verification of the optimization methodology is tested and performed for the 65-nm CMOS device. Compared with realistic fabricated and measured data, this approach can achieve the device characteristics; e.g., for the explored 65-nm n-type MOS field effect transistor, the on-state current > 0.35 mA/mum, the off-state current < 1.5e - 11 A/mum, and the threshold voltage = 0.43 V. Meanwhile, it reduces the threshold voltage fluctuation (sigma<sub>vth</sub> ~ 0.017 V). This approach provides an alternative to accelerate the tuning of process parameters and benefits manufacturing of nanoscale CMOS devices.
    IEEE Transactions on Semiconductor Manufacturing 12/2007; DOI:10.1109/TSM.2007.907623 · 0.98 Impact Factor
  • Yiming Li · Yi-Hui Chiang · Shao-Ming Yu · Su-Yun Chiang · C.-H. Hung
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    ABSTRACT: In this work, we apply an improvement dynamic model of the foreign direct investment (FDI) flow to analyze the evolution of FDI flow. In comparison with the fundamental growth model of FDI, the simulation result is further accurate if the asymmetric growth pattern and heterogeneity of the potential adopters are considered. According to the result, the internal influence dominates the growth of FDI flow from Taiwan to China during 2001-2006, taking the electronics industry for example.
    12/2007; DOI:10.1063/1.2835918
  • Source
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    ABSTRACT: In this paper, we numerically study the discrete-dopant-induced characteristic fluctuations in 16nm silicon-on-insulator (SOI) FinFETs. For devices under different temperature condition, discrete dopants are statistically generated and positioned into the three-dimensional channel region to examine associated carrier transportation characteristics, concurrently capturing “dopant concentration variation” and “dopant position fluctuation”. Electrical characteristics’ fluctuations are growing worse when the substrate temperature increases, the standard deviation of threshold voltage increases 1.75 times when substrate temperature increases from 300K to 400K for example. This “atomistic” device simulation technique is computationally cost-effective and provides us an insight into the problem of discrete-dopant-induced fluctuation and the relation between the fluctuation and thermal effect.
    11/2007: pages 365-368;
  • Yiming Li · Shao-Ming Yu · Hung-Ming Chen
    [Show abstract] [Hide abstract]
    ABSTRACT: In this paper, we investigate the threshold voltage fluctuation for nanoscale metal-oxide-semiconductor field effect transistor (MOSFET) and silicon-on-insulator (SOI) devices. The threshold voltage fluctuation comes from random dopant and short channel effects. The random-dopant-induced fluctuation is due to the random nature of ion implantation. The gate-length deviation and the line-edge roughness are mainly resulted from the short-channel effect. For the SOI devices, we should also consider the body thickness variation. In our investigation, the metal gate with high-κ material MOSFET is a good choice to reduce fluctuation of threshold voltage when comparing to the poly gate MOSFET and thin-body SOI devices.
    Microelectronic Engineering 09/2007; 84(9):2117-2120. DOI:10.1016/j.mee.2007.04.059 · 1.34 Impact Factor
  • [Show abstract] [Hide abstract]
    ABSTRACT: We have, for the first time, experimentally quantified random dopant distribution (RDD) induced V, standard deviation up to 40 mV for 20 nm-gate planar CMOS. Discrete dopants have been statistically positioned in the 3D channel region to examine associated carrier transportation characteristics, concurrently capturing "dopant concentration variation" and "dopant position fluctuation". As gate length further scaling down to 15 nm, the newly developed discrete-dopant scheme features an effective solution to suppress 3-sigma-edge single digit dopants induced V, variation by gate work function modulation. The extensive study may postpone the scaling limit projected for planar CMOS.
    VLSI Technology, 2007 IEEE Symposium on; 07/2007
  • Source
    Shih-Ching Lo · Yiming Li · Shao-Ming Yu
    [Show abstract] [Hide abstract]
    ABSTRACT: In this paper, an analytical solution of the Poisson equation for double-gate metal-semiconductor-oxide field effect transistor (MOSFET) is presented, where explicit surface potential is derived so that the whole solution is fully analytical. Based on approximations of potential distribution, our solution scheme successfully takes the effect of doping concentration in each region. It provides an accurate description for partially and fully depleted MOSFET devices in different regions of operation. Comparison with numerical data shows that the solution gives good approximations of potential for MOSFETs under different biases and geometry configurations. The solution can be applied to estimate classical and quantum electron density of nanoscale double-gate MOSFETs.
    Mathematical and Computer Modelling 07/2007; 46(1-2):180-188. DOI:10.1016/j.mcm.2006.12.018 · 2.02 Impact Factor
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    ABSTRACT: In this work, we propose an adaptive Monte Carlo (MC) simulation technique to compute the sample paths for the dynamical asset price. In contrast to conventional MC simulation with constant drift and volatility (mu,sigma), our MC simulation is performed with variable coefficient methods for (mu,sigma) in the solution scheme, where the explored dynamic asset pricing model starts from the formulation of geometric Brownian motion. With the method of simultaneously updated (mu,sigma), more than 5,000 runs of MC simulation are performed to fulfills basic accuracy of the large-scale computation and suppresses statistical variance. Daily changes of stock market index in Taiwan and Japan are investigated and analyzed.
    07/2007; DOI:10.1063/1.2759756
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    ABSTRACT: Nanoscale multiple-gate fin-typed field effect transistors (FinFETs) are promising candidates for next generation semiconductor devices. Impact of the discrete-dopant number and discrete-dopant position on device characteristics is crucial for nanoscale semiconductor devices. In this paper, we study the discrete-dopant-induced potential and threshold voltage fluctuations in 16nm triple-gate FinFET devices. Discrete dopants are statistically positioned into the three-dimensional channel region to examine associated carrier transportation characteristics, concurrently capturing ``dopant concentration variation'' and ``dopant position fluctuation''. It is found that the inhomogeneity of the potential induced by the discreteness of the channel dopants significantly disturbs device threshold voltage, and thus the device characteristics. This study provides an insight into the source of fluctuation and fluctuations induced by discrete dopants in ultra-small field effect transistors with vertical channel structures.
    06/2007; 922:387-390. DOI:10.1063/1.2759705
  • Shao-Ming Yu · Jam-Wen Lee · Yiming Li
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    ABSTRACT: In this paper we propose a silicide design consideration for electrostatic discharge (ESD) protection in nanoscale CMOS devices. According to our practical implementation, it is found that a comprehensive silicide optimization can be achieved on the gate, drain, and source sides with very few testkey designs. Our study shows that there is a high characteristic efficiency for various conditions; in particular, for optimizing the performance of sub-100 nm complementary metal-oxide-semiconductor devices in system-on-a-chip era.
    Microelectronic Engineering 02/2007; 84(2):213-217. DOI:10.1016/j.mee.2006.02.006 · 1.34 Impact Factor
  • Source
    Yiming Li · Shao-Ming Yu · Yih-Lang Li
    [Show abstract] [Hide abstract]
    ABSTRACT: In this paper, a simulation-based optimization technique for integrated circuit (IC) design automation is presented. Based on a genetic algorithm (GA), Levenberg-Marquardt (LM) method, and circuit simulator, a window-interfaced prototype of computer-aided design (CAD) is developed for IC design. Considering low noise amplifier (LNA) IC, we simultaneously evaluate specifications including S parameters, K factor, noise figure, and input third-order intercept point in the optimization process. If the simulated results meet the aforementioned constraints, the prototype outputs the optimized parameters. Otherwise, CAD activates GA for global optimization; simultaneously, LM method searches solutions with the results of GA. The prototype then calls a circuit simulator to compute and evaluate newer results until all specifications are matched. More than fifteen parameters including device sizes, passive components, and biasing conditions are optimized for the aforementioned constraints. For LNA IC with 0.18μm metal-oxide-silicon filed effect transistors, benchmark results confirm the functionality of the implemented prototype.
    Computational Science - ICCS 2007, 7th International Conference, Beijing, China, May 27 - 30, 2007, Proceedings, Part IV; 01/2007
  • Source
    Yiming Li · Chih-Hong Hwang · Shao-Ming Yu
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    ABSTRACT: We in this paper for the first time explore the static noise margin (SNM) of a six-transistor (6T) static random access memory (SRAM) cell with nanoscale silicon-on-insulator (SOI) fin-typed field effect transistors (FinFETs). The SNM is calculated with respect to the supply voltage, operating temperature, and cell ratio by performing a three-dimensional mixed-mode simulation. To include the quantum mechanical effect, the density-gradient equation is simultaneously solved in the coupled device and circuit equations. The standard deviation ( ¿ SNM ) of SNM versus device's channel length is computed, based upon the design of experiment and response surface methodology. Compared with the result of SNM for SRAM with 32nm planar metal-oxide-semiconductor field effect transistors, SRAM with SOI FinFETs quantitatively exhibits higher SNM and lower ¿ SNM . Improvement of characteristics resulting from good channel controllability implies that SRAM cells fabricated with FinFETs continuously maintains cell stability in sub-32nm technology nodes.
    Computational Science - ICCS 2007, 7th International Conference, Beijing, China, May 27 - 30, 2007, Proceedings, Part IV; 01/2007