Y. Tanji

Kagawa University, Takamatu, Kagawa, Japan

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Publications (52)5.11 Total impact

  • Y. Tanji, H. Kamei
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    ABSTRACT: The behavioral model of class E amplifiers on the steady-state are given based on the modified nodal analysis (MNA) formulation. The MNA formulation provides circuit equations which are adopted in general purpose circuit simulators such as SPICE. Hence, even though the circuit configuration is changed, the behavioral model can be easily obtained. To produce the behavioral model, the MOSFET including in the class E amplifier is replaced with an ideal switch. Each dynamical system depending on "on" and "off" states of the switch is categorized into the predictor system in control theory. Thus, the behavioral model of the class E amplifiers is obtained based on control theory.
    Power Electronics and Drive Systems (PEDS), 2013 IEEE 10th International Conference on; 01/2013
  • H. Matsushita, Y. Tanji
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    ABSTRACT: The class-E amplifier is one of the switching amplifiers, which satisfies the class-E switching conditions. It is, however, difficult to determine the values of the passive elements included in the circuit for achieving the class-E switching conditions. Recently, the Newton type algorithm is proposed to determine the passive elements. However, this method requires a good initial estimation. In this paper, an algorithm using Independent-minded Particle Swarm Optimization (IPSO) is introduced to estimate the initial conditions. To find it efficiently, the MOSFET in the class-E amplifier is replaced with an ideal switch and the objective function for the optimization is efficiently evaluated. Unfortunately, the objective function has multimodal characteristics and a robust optimization method is required. Then, the optimum solution is found by using IPSO which shows good performances for multimodal cases. Therefore, the initial estimation for the Newton type algorithm is easily obtained and a good design of the class-E amplifier becomes available.
    Soft Computing and Intelligent Systems (SCIS) and 13th International Symposium on Advanced Intelligent Systems (ISIS), 2012 Joint 6th International Conference on; 01/2012
  • Yuichi Tanji, Takayuki Watanabe
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    ABSTRACT: This paper presents generating stable and sparse reluctance/inductance matrix from the inductance matrix which is extracted under insufficient discretization. To generate the sparse reluctance matrix with guaranteed stability, the original matrix has to be (strictly) diagonally dominant M matrix. Hence, the repeated inductance extractions with a smaller grid size are necessary in order to obtain the well-defined matrix. Alternatively, this paper provides some ideas for generating the sparse reluctance matrix, even if the extracted reluctance matrix is not diagonally dominant M matrix. These ease the extraction tasks greatly. Furthermore, the sparse inductance matrix is also generated by using double inverse methods. Since reluctance components are not still supported in SPICE-like simulators, generating the sparse inductance matrix is more useful than the sparse reluctance one.
    IEICE Transactions. 01/2010; 93-C:379-387.
  • Yuichi Tanji
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    ABSTRACT: Fast interconnect simulation technique with SPICE level accuracy is presented in this paper. First, the nonlinear devices are separately expressed with the linear components in the Newton method. Using Woodbury's formula, the LU decomposition of the Jacobian matrix the elements of which are composed of the linear elements is only once done and factorization of the full Jacobian matrix is not necessary at each step of the Newton iteration. Therefore, the cost of the proposed method becomes several times of the simulation in which the linear components are only included, when the number of nonlinear elements is much less than the linear components, which is typical situation for interconnect analysis. It is confirmed that the proposed method is more efficient than Berkeley SPICE.
    International Symposium on Circuits and Systems (ISCAS 2010), May 30 - June 2, 2010, Paris, France; 01/2010
  • Source
    H. Sekiya, T. Ezawa, Y. Tanji
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    ABSTRACT: This paper presents novel design procedures for class E switching circuits allowing implicit circuit equations. Because of the allowance, circuit simulators can be used in the proposed design procedures. Moreover, the proposed design procedures also allow any conditions considered until now. The proposed design algorithms are implemented by using PSpice and OPTIMUS. This paper shows the design examples of two kinds of class E switching circuits. In particular, the design example of the class E oscillator shows the benefit of the proposed design procedure eminently, i.e., it is unnecessary to make an equivalent model of the semiconductor devices for the design. These design examples show the validity and effectiveness of the proposed design procedures.
    Circuits and Systems I: Regular Papers, IEEE Transactions on 01/2009; · 2.24 Impact Factor
  • Yuichi Tanji
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    ABSTRACT: The passive and sparse reduced-order modeling of a RLC network is presented, where eigenvalues and eigenvectors of the original network are used, and thus the obtained macromodel is more accurate than that provided by the Krylov subspace methods or TBR procedures for a class of circuits. Furthermore, the proposed method is applied to low pass filtering of a reduced-order model produced by these methods without breaking the passivity condition. Therefore, the proposed eigenspace method is not only a reduced-order macromodeling method, but also is embedded in other methods enhancing their performances.
    IEICE Transactions. 01/2008; 91-A:2419-2425.
  • Source
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    ABSTRACT: SUMMARY A fast time-domain simulation technique of plane circuits via two-layer Cellular Neural Network (CNN) -based modeling, which is necessary for power/signal integrity evaluation in VLSIs, printed circuit boards, and packages, is presented. Using the new notation expressed by the two-layer CNN, 1,553 times faster simulation is achieved, compared with Berkeley SPICE (ngspice). In CNN community, CNNs are generally simulated by explicit numerical integration such as the forward Euler and Runge-Kutta methods. However, since the two-layer CNN is a stiff circuit, we cannot analyze it by using an explicit numerical integration method. Hence, to analyze the two-layer CNN and reduce the computational cost, the leapfrog method is introduced. This procedure would open an applica-
    IEICE Transactions. 01/2008; 91-A:3757-3762.
  • Tadatoshi Sekine, Yuichi Tanji, Hideki Asai
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    ABSTRACT: This paper describes the matrix order reduction method by the nodal analysis formulation and the application of relaxation-based simulation technique to interconnect and plane networks. First, the characteristics of the power/ground plane networks are considered. Next, the formulation of the plane network by nodal analysis (NA) method is suggested. Furthermore, application and estimation results of the relaxation-based numerical analyses are shown. Finally, it is confirmed that the relaxationbased methods improved by the suggested formulation are much more efficient than the conventional direct-based methods.
    IEICE Transactions. 01/2008; 91-A:2450-2455.
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    ABSTRACT: This paper presents generating stable and sparse reluctance/inductance matrix from the inductance matrix which is extracted under insufficient discretization. So far, to generate the sparse reluctance matrix with guaranteed stability, this matrix has to be diagonally dominant M matrix. Hence, the repeated inductance extractions are necessary using a smaller grid size, in order to obtain the well-defined matrix. Alternatively, this paper provides some ideas for generating the sparse reluctance matrix, even if the extracted reluctance matrix is not diagonally dominant M matrix, precisely, the positive off-diagonal elements are even found. This eases the extraction tasks greatly. Furthermore, the sparse inductance matrix is also generated by using the practical and sophisticated double inverse methods, which is useful for the SPICE simulation, since reluctance components are not still supported in SPICE- like simulators.
    Proceedings of the 13th Asia South Pacific Design Automation Conference, ASP-DAC 2008, Seoul, Korea, January 21-24, 2008; 01/2008
  • A. Tsuzaki, T. Unno, Y. Tanji, H. Asai
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    ABSTRACT: This paper describes a fast transient simulation based on model order reduction and RLCG-MNA formulation, which has been proposed as the method to represent compactly RLCG interconnect and plane networks, instead of the standard modified nodal analysis (MNA). The proposed method is applied to the simulation of a simple example, and it is confirmed that not only the computational cost of the simulation but also the macro-modeling cost can be reduced.
    Circuit Theory and Design, 2007. ECCTD 2007. 18th European Conference on; 09/2007
  • Source
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    ABSTRACT: This paper presents a fast transient simulation method for power distribution networks (PDNs) of the PCB/Package. Because these PDNs are modeled as large-scale linear circuits consisting of a large number of RLC elements, it takes large costs to solve by conventional circuit simulators, such as SPICE. Our simulation method is based on the leapfrog algorithm, and can solve RLC circuits of PDNs faster than SPICE. Actual PDNs have frequency-dependent dispersions such as the skin-effect of conductors and the dielectric loss. To model these dispersions, more number of RLC elements are required, and circuit structures of these dispersion models are hard to solve by using the leapfrog algorithm. This paper shows that the circuit structures of dispersion models can be converted to suitable structures for the leapfrog algorithm. Further, in order to reduce the simulation time, our proposed method exploits parallel computation techniques. Numerical results show that our proposed method using single processing element (PE) enables a speedup of 20--100 times and 10 times compared to HSPICE and INDUCTWISE with the same level of accuracy, respectively. In a large-scale example with frequency-dependent dispersions, our method achieves over 94% parallel efficiency with 5PEs.
    IEICE Transactions. 01/2007; 90-A:388-397.
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    ABSTRACT: One or 2-step Gauss-Jacobi method is efficiently incorporated to the large scale interconnect analysis. In order to make the Gauss-Jacobi method within 1 or 2 iterations during each time step, the interconnect network is formulated by the RLCG-MNA formulation. In the numerical example, it is illustrated that the one-step Gauss-Jacobi method is 1,035 times faster than Berkeley SPICE and several tens times faster than INDUCTWISE which is known as the recent fast simulation method. Further, we show that the 2-step Gauss-Jacobi method is rational from efficiency and accuracy points of views.
    Quality Electronic Design, 2006. ISQED '06. 7th International Symposium on; 04/2006
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    ABSTRACT: A fast method for timing analysis of large scale RLC networks using the RLCG-MNA formulation, which provides good properties for fast matrix solvers, is presented. The proposed method is faster than INDUCTWISE and more general than the RLP algorithm, where INDUCTWISE and RLP algorithm are known as the state-of-art simulation methods. In the numerical example, good performances of the proposed method are illustrated compared with the previous works.
    Proceedings of the Conference on Design, Automation and Test in Europe, DATE 2006, Munich, Germany, March 6-10, 2006; 01/2006
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    ABSTRACT: A fast timing analysis of plane circuits via two-layer CNN-based modeling, which is necessary for the solution of power/signal integrity problems in printed circuit boards and packages, is presented. Using the new notation expressed by the two-layer CNN, more than 1500 times faster simulation is achieved, compared with Berkeley SPICE (ngspice). In CNN community, CNNs are generally simulated by explicit numerical integration algorithms such as the forward Euler and Runge-Kutta methods. However, since the system of the two-layer CNN becomes stiff, we cannot analyze the CNN by using an explicit numerical integration algorithm. Hence, to analyze the two-layer CNN and reduce the computational cost, the leapfrog method is introduced in this paper. This procedure would open a CNN application up to electronic design automation area
    International Symposium on Circuits and Systems (ISCAS 2006), 21-24 May 2006, Island of Kos, Greece; 01/2006
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    ABSTRACT: In this paper, we show the generalized method of the time-domain circuit simulation based on LIM. Our method is applicable to any structure of circuits by combination with the SPICE-like method. In order to show the validity and efficiency of our method, an example circuit is simulated and the proposed method is compared with the conventional ones.
    01/2006;
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    ABSTRACT: In this paper, we focus on the verification of the PCB/Package power integrity, which becomes very important for the design of state-of-art high speed digital circuits. The simulation of power distribution networks (PDNs) of the PCB/Package, which can be modeled as a large number of RLC lumped components, is a time-consuming task for using the conventional circuit simulator, such as SPICE. For this problem, we propose a parallel-distributed time-domain circuit simulation algorithm based on LIM. Furthermore, an effective modeling of frequency-dependencies of the PDNs, such as skin effects and dielectric losses, to solve by LIM is proposed.
    Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, Yokohama, Japan, January 24-27, 2006; 01/2006
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    ABSTRACT: This paper describes efficient generation of reduced-order interconnect macromodels using a new MNA formulation and Krylov subspace methods. The proposed method generates the model ten times faster than PRIMA.
    Electrical Performance of Electronic Packaging, 2005. IEEE 14th Topical Meeting on; 11/2005
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    ABSTRACT: In this paper, we show the generalized method of the time-domain circuit simulation based on LIM. First, the formulation of the circuit for LIM is modified and generalized. Furthermore, the modified simulation algorithm is suggested. As a result, our method is applicable to any structure of circuits. Some example circuits are simulated and the proposed method is compared with the conventional ones, in order to show the validity and efficiency of our method
    Custom Integrated Circuits Conference, 2005. Proceedings of the IEEE 2005; 10/2005
  • Y. Tanji, H. Kubota
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    ABSTRACT: The passive approximation of tabulated frequency-data for modeling package, PCB, and integrated circuits is presented. The macromodels in the Laplace-domain are directly obtained by the Fourier series approximation of the frequency-data and are represented using a Laguerre basis. The rigorous proof of passivity preservation associated with the proposed models is provided.
    Circuits and Systems, 2005. ISCAS 2005. IEEE International Symposium on; 06/2005
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    ABSTRACT: SUMMARY In this paper, we propose a new algorithm for calculating the exact poles of the admittance matrix of RLCG interconnects. After choosing dominant poles and corresponding residues, each element of the exact admittance matrix is approximated by partial fraction. A procedure to obtain the residues that guarantee the passivity is also provided, based on experimental studies. In the procedure the residues are calculated by using the least squares method so that the partial fraction matches each element of the exact admittance matrix in the frequency-domain. From the partial fraction representation, the asymptotic equivalent circuit models which can be easily simulated with SPICE are synthesized. It is shown that an efficient model-order reduction is possible for short-length interconnects.
    IEICE Transactions. 01/2005; 88-A:513-523.

Publication Stats

105 Citations
5.11 Total Impact Points

Institutions

  • 2002–2013
    • Kagawa University
      • Department of Reliabilitybased Information Systems Engineering
      Takamatu, Kagawa, Japan
  • 2009
    • Chiba University
      • Graduate School of Advanced Integration Science
      Chiba-shi, Chiba-ken, Japan
  • 2005–2007
    • Shizuoka University
      • Department of Mathematical and Systems Engineering
      Shizuoka-shi, Shizuoka-ken, Japan
  • 1999–2002
    • Sophia University
      • • Department of Engineering and Applied Science
      • • Division of Electrical and Electronics Engineering
      Tokyo, Tokyo-to, Japan
  • 1998
    • The University of Tokushima
      • Department of Electrical and Electronic Engineering
      Tokushima-shi, Tokushima-ken, Japan