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ABSTRACT: In this study, a new technique to extract the S/D series resistance (R<sub>sd</sub>) from the total resistance versus transconductance gain plot R<sub>tot</sub>(1/beta) is proposed. The technique only requires the measurement of I<sub>d</sub>(V<sub>gs</sub>)|<sub>Vgt</sub> and beta, allowing fast and statistical analysis in an industrial context. Unlike the usual R<sub>tot</sub>(L)-based techniques, it has the advantage of being insensitive to the channel length and mobility variations and finally enables to extract very accurate values for R<sub>sd</sub>(V<sub>gs</sub>) and the effective mobility reduction factor mu<sub>eff</sub>(V<sub>gt</sub>)/mu<sub>eff</sub>(0).
VLSI Technology, Systems, and Applications, 2009. VLSI-TSA '09. International Symposium on; 05/2009
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ABSTRACT: The length of MOSFET channels is an important circuit design parameter, and this paper focuses on a new industrially-compatible technique using gate-to-channel measurements C<sub>gc</sub>(V<sub>g</sub>) to provide accurate extraction of the channel length. Thanks to fully-automatic probers, the technique provides large scale extractions and so, statistical-based results can be extracted with a maximized reliability. An in-depth study of parasitic capacitances has been performed to improve the extraction accuracy to within a few nanometers.
IEEE Transactions on Semiconductor Manufacturing 12/2008; · 0.72 Impact Factor
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ABSTRACT: We developed a new Y-function-based extraction methodology to overcome the difficulties encountered by applying the conventional techniques. Our method relies on a robust recursive algorithm which requires a limited number of input parameters on which the results have a weak dependence, and so an increased reliability. The obtained results are in line with the previous methods, but show an improved accuracy. Finally, parameter extraction performed through this technique has provided accurate and reliable results over a large range of MOSFET architectures.
Microelectronic Test Structures, 2008. ICMTS 2008. IEEE International Conference on; 04/2008
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ABSTRACT: The occurence of periodic Coulomb blockade in transistors at low temperature allows to extract the capacitances between the channel and the gate, source, and drain. This extremely sensitive method is well adapted to nanoscale devices, where these capacitances are well below the fF range and in parallel with low resistances. We applied this method to 3-D stacked MOSFETs featuring a double-gate top channel and a single-gate bottom channel. The measured gate capacitances are in excellent agreement with estimations based on the geometry, and are independent on the gate voltage. The source and drain capacitances can also be measured separately for each parallel conduction channel, even when their values are markedly different. We illustrate this case with a device with one dominating double-gate channel and a buried, single-gate channel which is not detectable at 300 K and contributes for less than 5% to the total conductance at 4.2 K.
IEEE Transactions on Nanotechnology 02/2008; · 2.29 Impact Factor
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C. Fenouillet-Beranger,
S. Denorme,
B. Icard,
F. Boeuf,
J. Coignus,
O. Faynot,
L. Brevard,
C. Buj,
C. Soonekindt,
J. Todeschini, [......],
D. Galpin,
D. Pop,
R. Delsol,
R. Pantel,
F. Pionnier,
G. Thomas,
D. Bensahel,
S. Deleombus,
T. Skotnicki,
H. Mmgam
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ABSTRACT: In this paper, we report on FD-SOI with high-k and single metal gate as a possible candidate for the 32 nm LOP and LSTP nodes. Good I<sub>on</sub>/I<sub>off</sub> performance for nMOS and pMOS transistors in the ultra-low-leakage regime (I<sub>off</sub>=6.6 pA/μm) are presented. In addition co-integration of high voltage devices with EOT 29A/V<sub>dd</sub> 1.8 V are made. For the first time, the functionality of 0.248 μm and 0.179 μm<sup>2</sup> 6T-SRAM bit-cells is demonstrated on FDSOI technology with a high-k/metal gate stack.
Electron Devices Meeting, 2007. IEDM 2007. IEEE International; 01/2008
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ABSTRACT: As SRAM integration scheme becomes more and more aggressive in term of development time, supply voltage and geometric dimension, parameter extraction techniques need to be continuously upgraded to ensure the best support for technology development. An innovative approach for write-margin extraction has recently been published at the ISSCC'2006 conference. This approach makes use of test structure giving access to internal node. Here, this approach is evaluated through our 65 nm process and it is shown that the layout and probing of the innovative test structure induces a write delay. As a consequence an adaptation of this innovative methodology is proposed. The new combined solution gives promising results, in terms of accuracy and spread, to better follow the process development of advanced SRAM.
Microelectronic Test Structures, 2007. ICMTS '07. IEEE International Conference on; 04/2007
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ABSTRACT: Constant downscaling of transistors leads to increase the relative difference between L<sub>mask</sub> and L<sub>eff</sub>. Effective length (L<sub>eff</sub>) extractions are now crucial to avoid calculations errors on parameters such as the mobility, which can exceed 100% for shorter devices. We propose an industrially-adapted method to extract L<sub>eff</sub> by using an enhanced "split C-V" method. Accurate and consistent values have been extracted (plusmn1 nm) and then correlated to mobility and HCI lifetime studies, as a function of L<sub>eff</sub>.
Microelectronic Test Structures, 2007. ICMTS '07. IEEE International Conference on; 04/2007
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A. Cros,
K. Romanjek,
D. Fleury,
S. Harrison,
R. Cerutti,
P. Coronel,
B. Dumont,
A. Pouydebasque,
R. Wacquez,
B. Duriez,
R. Gwoziecki,
F. Boeuf, H. Brut,
G. Ghibaudo,
T. Skotnicki
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ABSTRACT: A new mobility degradation specific to short channel MOSFETs is studied and elucidated. Pocket implants/dopants pile-up, interface states/oxide charges, remote Coulomb scattering or ballisticity are insufficient to explain this degradation. The role of non-Coulombian (neutral) defects, which can be healed by increasing the annealing temperature, is evidenced
Electron Devices Meeting, 2006. IEDM '06. International; 01/2007
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ABSTRACT: Double gate type transistors are needed for the ultimate integration on silicon, and thus extraction techniques have to be adapted. In this paper, the influence of the series resistance on the extrinsic mobility reduction parameters is analysed, in the case of a resistance varying with the gate bias. It is evidenced that both the low field and high field parameters are impacted. Then, a new approach is proposed for the extraction of the series resistance variation with the gate voltage, and applied to the analysis of gate-all-around transistors series resistance, with doped and undoped body.
Microelectronic Test Structures, 2005. ICMTS 2005. Proceedings of the 2005 International Conference on; 05/2005
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B. Duriez,
B. Tavel,
R. Boeuf,
M.T. Basso,
Y. Laplanche,
C. Ortolland,
D. Reber,
R. Wacquant,
P. Morin,
D. Lenoble, [......],
D. Roy,
M. Marin,
F. Payet,
N. Cagnat,
R. Difrenza,
K. Rochereau,
M. Denais,
P. Stolk,
M. Woo,
F. Arnaud
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ABSTRACT: This paper demonstrates a full gate stack optimization by using post gate anneal (PGA) solution coupled with both germanium and fluorine gate predoping. We obtained a large carrier mobility enhancement for both NMOS (+50%) and PMOS (+20%) thanks to an important biaxial tensile stress generated by Ge predoping. Very simple and epitaxy-free, this architecture is directly compatible with both low power and high performance transistors. Competitive IonN = 1000μA/μm and IonP = 400μA/μm were found for Ioff = 100nA/μm at IV Vdd operation. Attractive matching factor A<sub>VT</sub> lower than 2.5 mV·μm has been obtained with poly grain size optimization. NBTI criteria have been successfully achieved thanks to a complementary Fluorine implant inside the P+ gate.
Electron Devices Meeting, 2004. IEDM Technical Digest. IEEE International; 01/2005
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F. Arnaud,
B. Duriez,
B. Tavel,
L. Pain,
J. Todeschini,
M. Jurdit,
Y. Laplanche,
F. Boeuf,
F. Salvetti,
D. Lenoble, [......],
D. Roy,
M. Denais,
K. Rochereau,
R. Difrenza,
N. Planes, H. Brut,
L. Vishnobulta,
D. Reber,
P. Stolk,
M. Woo
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ABSTRACT: A 65nm CMOS platform employing General Purpose (GP) and Low Power (LP) devices and 0.5 μm<sup>2</sup> 6T-SRAM bit-cells was developed using both conventional design and low cost CMOS process flow incorporating a strained silicon solution. Fully working 0.5 μm<sup>2</sup> bit-cells with 240mV of SNM and 35 μA of cell current at 1.2V operation were obtained. The GP transistor drive currents of 875 μA/ μm and 400 μA/ μm for NMOS and PMOS respectively are obtained at V<sub>dd</sub> = 1V, Ioff = 100nA/um. Using the same CMOS flow, 65nm analog transistor parameters are derived for the first time, showing Vt matching (Avt=2.2mV. μm) and analog voltage gain factor (G<sub>m</sub>/G<sub>d</sub>>2000 for L = 10 μm) at the leading edge for this process technology. NBTI criteria at 125°C for both LP and GP transistors are presented and characterized at overdrive conditions.
VLSI Technology, 2004. Digest of Technical Papers. 2004 Symposium on; 07/2004
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ABSTRACT: Measurement of dark current and capacitance of pixel array are fundamental in the development of new sensor technologies. These parameters are usually very low and require large structures to be accurately measured. This is area consuming and, in any case, needs the use of high-resolution semi-automatic test bench. In this paper, a new methodology based on a capacitance discharge measurement is proposed and validated by comparison to direct measurements. It offers a small structure need, a low-test time and a high resolution, and can also be implemented on full automatic test bench for in-line monitoring.
Microelectronic Test Structures, 2004. Proceedings. ICMTS '04. The International Conference on; 04/2004
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ABSTRACT: Characterization, modelling and monitoring of interconnect capacitance are of first interest for CMOS and BiCMOS technology development, especially for circuit delay evaluation. An improvement of the Single Pattern Driver method is proposed in this paper to take into account MOST intrinsic and diode leakages which can introduce errors of the order of few hundred aF in advanced nanometer technologies. The accuracy is hugely improved and reaches now 10aF.
Microelectronic Test Structures, 2004. Proceedings. ICMTS '04. The International Conference on; 04/2004
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B. Tavel,
M. Bidaud,
N. Emonet,
D. Barge,
N. Planes, H. Brut,
D. Roy,
J.C. Vildeuil,
R. Difrenza,
K. Rochereau, [......],
S. Bruyere,
C. Parthasarthy,
N. Revil,
R. Pantel,
F. Guyader,
L. Vishnubotla,
K. Barla,
F. Arnaud,
P. Stolk,
M. Woo
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ABSTRACT: This work shows the benefits of using plasma nitrided gate oxide which supports the gate leakage requirements for 65 nm platform development. Electrical data shows gate leakage to be reduced by half a decade compared to conventional NO processing with Ioff at 3nA/um, Vdd=0.9 V for 65 nm general purpose requirements. Extensive device characterization of the plasma nitride process is presented where the reduction in gate leakage offers benefits in terms of a 4× reduction in static power, a 6% reduction in dynamic power consumption, comparative analog performance and improved reliability.
Electron Devices Meeting, 2003. IEDM '03 Technical Digest. IEEE International; 01/2004
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S. Harrison,
P. Coronel,
F. Leverd,
R. Cerutti,
R. Palla,
D. Delille,
S. Borel,
S. Jullian,
R. Pantel,
S. Descombes, [......],
A. Talbot,
A. Villaret,
S. Monfray,
P. Mazoyer,
J. Bustos, H. Brut,
A. Cros,
D. Munteanu,
J.-L. Autran,
T. Skotnicki
[show abstract]
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ABSTRACT: Utilizing the SON (silicon on nothing) process, highly performant double gate devices have been processed in a planar configuration. Two families of devices were obtained (high performance and low power) with very high Ion/Ioff trade off. Drive currents of 1954 μA/μm (Ioff = 283 nA/μm) and 1333 μA/μm (Ioff = 1 nA/μm) are obtained at 1.2 V with Tox = 20 Å and Lgate = 70 nm. DIBL is very well controlled, measured below 60 mV for gates as short as 40 nm. These features place our devices among the most performant ever reported.
Electron Devices Meeting, 2003. IEDM '03 Technical Digest. IEEE International; 01/2004
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B. Froment,
M. Muller, H. Brut,
R. Pantel,
V. Carron,
H. Achard,
A. Halimaoui,
F. Boeuf,
F. Wacquant,
C. Regnier, [......],
S. Lis,
V. Tirard,
P. Morin,
F. Trentesaux,
V. Gravey,
T. Mandrekar,
D. Rabilloud,
S. Van,
E. Olson,
J. Diedrick
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ABSTRACT: In this work, NiSi SALICIDE has been fully integrated with sub-50 nm gate length transistors and compared to its CoSi<sub>2</sub> counterpart. Nickel thickness has been reduced to target the CoSi<sub>2</sub> sheet resistance. It was found that NiSi layers basic lattice planes with vertical orientation are often observed inside the grains. NiSi-based CMOS transistors show the same performance as CoSi2-transistors, but nickel can also silicide very narrow poly lines whereas cobalt can not. Moreover, NiSi reduces the STI diode-leakage perimeter, but increases channel side leakage, where CoSi<sub>2</sub> shows a "Schottky behavior". Thus we show that nickel allow MOS transistor scaling for future technology.
European Solid-State Device Research, 2003 33rd Conference on. ESSDERC '03; 10/2003
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F. Arnaud,
F. Boeuf,
F. Salvetti,
D. Lenoble,
F. Wacquant,
C. Regnier,
P. Morin,
N. Emonet,
E. Denis,
J.C. Oberlin, [......],
B. Hinschberger,
R. Pantel,
N. Revil,
C. Parthasarathy,
N. Planes, H. Brut,
J. Farkas,
J. Uginet,
P. Stolk,
M. Woo
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ABSTRACT: This work highlights a 65 nm CMOS technology platform for low power and general-purpose applications. A 6-T SRAM cell size of 0.69 μm<sup>2</sup> with a 45 nm gate length is demonstrated. Electrical data of functional SRAM bit-cell is presented at V<sub>dd</sub>=0.9 Volt using a conventional nitrided gate oxide dielectric. A comparison between offset spacer and PLAsma Doping (PLAD) is made for the transistor characteristics with very promising V<sub>th</sub>-L<sub>d</sub> and V<sub>th</sub>-W<sub>d</sub> profiles measured. Lithography employed a combination of both optical lithography and e-beam imaging. The BEOL integration used a conventional low K dielectric with copper metallization.
VLSI Technology, 2003. Digest of Technical Papers. 2003 Symposium on; 07/2003
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ABSTRACT: The impact of the gate leakage current on long MOS transistor characterization is investigated in this paper. Particularly for first order parameter extraction, a new method is proposed here to rid the gate current on advanced technologies with thin gate oxides. In linear and in strong inversion regimes, we first demonstrate experimentally a 50/50 partition of the gate current between source and drain nodes. TCAD simulations performed for several oxide thicknesses and biases also confirm this partition. The intrinsic channel current of the MOS transistor can then be isolated to extract first order parameters, especially in the case of large area devices which strongly suffer from gate leakage. We show that this I<sub>G</sub> correction permits to extract these parameters in a more consistent way. Finally, we evaluate the extraction error induced by the gate leakage current for varying oxide thicknesses and channel lengths.
Microelectronic Test Structures, 2003. International Conference on; 04/2003
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F. Arnaud,
F. Boeuf,
F. Salvetti,
D. Lenoble,
F. Wacquant,
C. Regnier,
P. Morin,
N. Emonet,
E. Denis,
J. C. Oberlin, [......],
B. Hinschberger,
R. Pantel,
N. Revil,
C. Parthasarathy,
N. Planes, H. Brut,
J. Farkas,
J. Uginet,
P. Stolk,
M. Woo
01/2003: pages 65-66; , ISBN: 4-89114-033-X
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ABSTRACT: To face the SIA roadmap constraints, the natural benefits of the SOI devices should be combined with aggressive scaling. The main ingredients for optimizing the SOI-MOSFETs architecture are film and gate oxide thickness, doping profiles (channel, halos and LDD regions) and lateral isolation techniques. In this paper, we show that the characteristics of floating body SOI devices are modified at low drain voltage by a gate to body current when the gate oxide thickness is as low as 2 nm. Carrier recombination and transconductance measurements versus gate voltage show that the modifications depend both on the geometries and device architecture (doping profiles).
SOI Conference, IEEE International 2002; 11/2002
