Kiran Puttegowda

Virginia Polytechnic Institute and State University, Blacksburg, Virginia, United States

Are you Kiran Puttegowda?

Claim your profile

Publications (7)0.84 Total impact

  • Source
    K. Puttegowda, G. Verma, S. Bali, R.M. Buehrer
    [Show abstract] [Hide abstract]
    ABSTRACT: We study the effect of cancellation order on bit error rate (BER) performance of a code division multiple access (CDMA) system employing a linear successive interference cancellation (SIC) receiver in both an additive white Gaussian noise (AWGN) channel and a Rayleigh fading channel. Four different ordering schemes are studied. We show that changing the cancellation order can lead to a significant change in the BER performance.
    Vehicular Technology Conference, 2003. VTC 2003-Fall. 2003 IEEE 58th; 11/2003
  • Source
    [Show abstract] [Hide abstract]
    ABSTRACT: A distinguishing feature of reconfigurable computing over rapid prototyping is its ability to configure the computational fabric on-line while an application is running. Conventional reconfigurable computing platforms utilize commodity FPGAs, which typically have relatively long configuration times. Shrinking the configuration time down to the nanosecond region opens possibilities for rapid context switching and virtualizing the computational resources. An experimental context-switching FPGA, called the CSRC, has been created by BAE Systems, and gives researchers the opportunity to explore context-switching applications. This paper presents results obtained from constructing both control-driven and data-driven context switching applications on the CSRC device, along with unique properties of the run-time and compile-time environment.
    The Journal of Supercomputing 10/2003; 26(3):239-257. · 0.84 Impact Factor
  • [Show abstract] [Hide abstract]
    ABSTRACT: In this paper we study the e#ect of cancellation order on bit error rate (BER) performance of a Code Division Multiple Access (CDMA) system employing a linear Successive Interference Cancellation (SIC) receiver in both an Additive White Gaussian Noise (AWGN) channel and a Rayliegh fading channel. Four di#erent ordering schemes are studied. We show that changing the cancellation order can lead to a significant change in the BER performance.
    08/2003;
  • Source
    K. Puttegowda, P. Athanas
    [Show abstract] [Hide abstract]
    ABSTRACT: Modular arithmetic is typically the computational bottleneck in a hardware implementation of public key cryptography algorithms. This paper focuses on an implementation of modular multiplication on the Quicksilver COSM adaptive computing machine as a run-time-reconfigurable user authentication context candidate. The design is targeted specifically to the COSM adaptive computing machine, taking into account the underlying architecture of the device.
    Field-Programmable Custom Computing Machines, 2003. FCCM 2003. 11th Annual IEEE Symposium on; 05/2003
  • [Show abstract] [Hide abstract]
    ABSTRACT: Advances in the field of bio-technology has led to an ever increasing demand for computational resources to rapidly search large databases of genetic information. Databases with billions of data elements are routinely compared and searched for matching and near-matching patterns. We present a system developed to search DNA sequence data using run-time reconfiguration of field programmable gate arrays (FPGAs). The system provides an order of magnitude increase in performance while reducing hardware complexity when compared to existing commercial systems.
    VLSI Design, 2003. Proceedings. 16th International Conference on; 02/2003
  • Source
    [Show abstract] [Hide abstract]
    ABSTRACT: One property that distinguishes reconfigurable computing from rapid prototyping is the ability to configure the computational fabric on-line while an application is running. Conventional reconfigurable computing platforms utilize commodity FPGAs, which typically have relatively long configuration times. Shrinking the configuration time down to the nanosecond region opens possibilities for rapid context switching and virtualizing the computational resources. An experimental context switching FPGA, called the CSRC, has been created by BAE Systems, and gives researchers the opportunity to explore context-switching applications. This paper presents results obtained from constructing both control-driven and data-driven context switching applications on the CSRC device, along with unique properties of the run-time and compile-time environment. 1
    06/2002;
  • Kiran Puttegowda
    [Show abstract] [Hide abstract]
    ABSTRACT: A distinctive feature of run-time reconfigurable systems is the ability to change the configurationof programmable resources during execution. This opens a number of possibilities suchas virtualisation of computational resources, simplified routing and in certain applicationslower power. Seamless run-time reconfiguration requires rapid configuration. Commodityprogrammable devices have relatively long configuration time, which makes them poor candidatesfor run-time reconfigurable systems....
    05/2002;