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ABSTRACT: In this paper we propose and validate a simple approach to empirically account for quantum effects in the transport direction of MOS transistors (i.e. source and drain tunneling and delocalized nature of the carrier wavepacket) in multi-subband Monte Carlo simulators, that already account for quantization in the direction normal to the semiconductor-oxide interface by solving the 1D Schrödinger equation in each section of the device. The model has been validated and calibrated against ballistic non-equilibrium Green's function simulations over a wide range of gate lengths, voltage biases and temperatures. The proposed model has just one adjustable parameter and our results show that it can achieve a good agreement with the NEGF approach.
Semiconductor Science and Technology 04/2010; 25(5):055011. · 1.72 Impact Factor
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ABSTRACT: In this paper we use a Multi-Subband-Monte-Carlo model to study the transport in nMOSFETs featuring strained silicon channels. It is shown that state-of-the-art modeling of the mobility in n-type inversion layers cannot reproduce the mobility enhancements measured in Si devices with either uniaxial or biaxial strain. Possible reasons for this limitation are analyzed in detail.
Journal of Computational and Theoretical Nanoscience 05/2008; 5(6):1106-1114. · 0.91 Impact Factor
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ABSTRACT: This paper presents a new self-consistent multisubband Monte Carlo model for electronic transport in the inversion layer of decananometric MOSFETs. The simulator is 2D in real space and in k-space and accounts for the electron-gas degeneracy in the k-space. Simulation of nanoscale ultra-thin-body silicon-on-insulator MOSFETs shows that the subband structure and the carrier degeneracy strongly affect the transport properties and, in particular, the injection velocity and the channel back-scattering
IEEE Transactions on Electron Devices 06/2007; · 2.32 Impact Factor
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ABSTRACT: This paper examines, by means of multi-subband-Monte-Carlo (MSMC) simulations, the prediction of the well known compact formula for back-scattering in nanoMOSFETs, analyzing the effect of carrier degeneracy and complex scattering mechanisms on the back-scattering. The paper also addresses the definition of an appropriate mean-free-path and its relationship to the low-field mobility
Electron Devices Meeting, 2006. IEDM '06. International; 01/2007
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ABSTRACT: In this paper, the authors use multi-subband-Monte-Carlo simulations to investigate the on-current increment induced by biaxial strain in n-MOSFETs featuring bulk and double-gate architecture with 25nm gate length. The effect of different scattering mechanisms and of the subband structure is analyzed in detail
Solid-State Device Research Conference, 2006. ESSDERC 2006. Proceeding of the 36th European; 10/2006
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ABSTRACT: In this paper, two Monte-Carlo simulators implementing different models of the influence of carrier quantization on the electrostatics and transport are applied to sub-100nm double-gate SOI devices. To this purpose a new stable and efficient scheme to implement the contacts in the simulation of DG SOI devices is introduced first. Then, results in terms of drain current and microscopic quantities are compared, providing a comparison between a well assessed semiclassical tool and a more rigorous multi-subband code
Solid-State Device Research Conference, 2006. ESSDERC 2006. Proceeding of the 36th European; 10/2006
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ABSTRACT: This paper presents a new self-consistent MC simulator for the 2D electron gas of nano-MOSFETs. The simulator is two-dimensional in real space and in k-space, and accounts for the electron gas degeneracy in the k-plane. Simulations of thin-film SOI MOSFETs show that the subband structure and the carrier degeneracy strongly affect the transport properties particularly the injection velocity. Our results also point-out the strong anisotropy of the occupation function, which seriously hampers the use of simulators based on the momentum of the BTE
Electron Devices Meeting, 2005. IEDM Technical Digest. IEEE International; 01/2006
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ABSTRACT: A Monte-Carlo simulator for the quasi-2D electron gas in the inversion layer of bulk and SOI MOSFETs has been developed. The code has been used to validate the momentum-relaxation-time technique, commonly used to evaluate the low field mobility, pointing out the importance of inter-subband transitions in SOI devices. The high field transport properties in thin SOI MOSFETs have been investigated, showing for the first time that surface roughness scattering could have a strong impact on the saturation velocity whose value is significantly lower than the value reported for bulk silicon and bulk MOSFETs. On the other hand, the high energy carrier distribution is only weakly influenced by carrier quantization.
Solid-State Device Research conference, 2004. ESSDERC 2004. Proceeding of the 34th European; 10/2004
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ABSTRACT: Electron and hole trapping were studied in sub-2-nm SiO<sub>2</sub>/Al<sub>2</sub>O<sub>3</sub>/poly-Si gate stacks. It was found that during substrate injection, electron trapping is the dominant mechanism. Conversely, during gate injection both hole and electron trapping can be observed, depending on the applied bias. These hot carrier effects are closely linked to the band structure of SiO<sub>2</sub>/Al<sub>2</sub>O<sub>3</sub>/poly-Si system.
IEEE Electron Device Letters 06/2004; · 2.85 Impact Factor
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ABSTRACT: In this paper, we report measurements of electron effective mobility (μ<sub>eff</sub>) in ultra-thin (UT) pure SiO<sub>2</sub> bulk MOSFETs. A low substrate doping was intentionally used to better detect a possible μ<sub>eff</sub> degradation at small T<sub>ox</sub>. New quantitative criteria were developed and used to obtain μ<sub>eff</sub> measurements unaffected by either gate doping penetration or gate oxide leakage. Mobility simulations, based on an improved and comprehensive remote Coulomb scattering (RCS) model, exhibit a good agreement with the experimentally observed mobility reduction at small T<sub>ox</sub>. Our results indicate that polysilicon screening is an essential ingredient to reconcile the RCS models with the experiments.
Electron Devices Meeting, 2003. IEDM '03 Technical Digest. IEEE International; 01/2004
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M. Heyns,
S. Beckx,
H. Bender,
P. Blomme,
W. Boullart,
B. Brijs,
R. Carter,
M. Caymax,
M. Claes,
T. Conard, [......],
Y. Manabe,
Y. Shimamoto,
P. Bajolet,
H. De Witte,
J.W. Maes,
L. Date,
D. Pique,
B. Coenegrachts,
J. Vertommen,
S. Passefort
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ABSTRACT: High-k dielectric layers are deposited using ALD or MOCVD. Most of the work focused on Hf-based high-k dielectrics, either as pure HfO<sub>2</sub>, as silicate or mixed with Al<sub>2</sub>O<sub>3</sub>. In some cases nitrogen is added to improve the high-temperature stability. Various surface preparation methods and deposition conditions are tested. Compatibility of the high-k stacks with poly-Si and metal electrodes is investigated. Significant improvements in yield and thermal stability are obtained by optimized modifications of the high-k stack. Scaling of the equivalent oxide thickness (EOT) is accomplished by implementing novel ideas in interface engineering and high-k materials processing. High-k stacks are tested in transistor structures with small gate lengths. The origin of the electrical instabilities and the observed drive current degradation of high-k transistors as compared to the SiO<sub>2</sub> reference transistors are studied in detail.
VLSI Technology, Systems, and Applications, 2003 International Symposium on; 02/2003
