K. Hunt

BAE Systems, Londinium, England, United Kingdom

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Publications (11)1.46 Total impact

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    ABSTRACT: BAE Systems, under contract to the US Air Force Research Labs, has been developing a 4Mb Non-Volatile Chalcogenide Random Access Memory (C-RAM¿) optimized for the radiation environments encountered in spacecraft applications. C-RAM is a phase change memory with a unique combination of features that collectively provide a high-density, low-power, non-volatile memory solution that is radiation hardened and meets rigorous reliability requirements. The device is now undergoing QML qualification in preparation for being flight production ready in early 2009. Flight qualified C- RAM will serve the critical need for rad hard non-volatile RAM in strategic space and military applications. Initial space radiation effects testing (heavy ion induced upset rates) demonstrate the robust nature of the device. No memory cell upsets were recorded and the majority of the observed upsets were soft errors (SE) induced in the sense amp circuits which are easily correctable with common error correcting code (ECC) algorithms. During the product development phase potential failure mechanisms associated with phase change memories such as proximity disturbs and drill-in effects were evaluated to determine whether they were legitimate concerns for C-RAM. These tests and other tests involving second order radiation effects, such as the effect of heavy ion radiation exposure on data retention lifetime were conducted. The results of these investigations further demonstrate the full capacity of the product technology. This paper will describe the C-RAM design and operation, and the results of the test and characterization of C-RAM devices.
    Non-Volatile Memory Technology Symposium, 2008. NVMTS 2008. 9th Annual; 12/2008
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    ABSTRACT: A 4 Mbit non-volatile chalcogenide-random access memory (C-RAM<sup>TM</sup>) has been designed and fabricated in RH 25, a radiation hardened CMOS technology. The top-down design focused on accommodating chalcogenide process variations and satisfying space system specifications. The optimized band-gap circuit supplies reference current and voltage that meet temperature and voltage requirements. The innovative write circuitry supplies appropriate currents (amplitude and shape) to the chalcogenide memory cells to allow them to be programmed either in amorphous state (write "0") or crystalline state (write "1"). The on-chip pulse generator circuit can provide multiple pulse widths for write "0" and write "1". The write circuits have a dedicated power supply, which can be removed to place the part in a read only mode. The read circuitry includes a voltage limiting circuit, an adjustable current reference, an adjustable pre-charge circuit, and a sense amplifier to accurately sense the current difference between cells programmed as "0" or "1". A localized, redundant cell architecture is implemented with shared read/write circuits to improve yield without impacting access times. The redundant cells can be tested prior to laser fusing or used to monitor endurance. Considerations for testability such as direct chalcogenide cell access, margin testing, analog monitors, and endurance acceleration have been implemented. Noise and power reduction techniques have also been used globally.
    Non-Volatile Memory Technology Symposium, 2006. NVMTS 2006. 7th Annual; 12/2006
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    ABSTRACT: The first generation of C-RAM memory is designed to greatly exceed (in density, write speed, endurance) the existing non-volatile memory solutions for space and to close the gap that exists between system requirements and availability. Based on the success of the 64kb C-RAM program, a 4Mb C-RAM prototype has been designed and fabricated in 0.25 mum radiation-hardened CMOS. In this paper we present a description of the 4Mb design as well as results of recent characterization and radiation test of the first pass of prototype parts
    Non-Volatile Memory Technology Symposium, 2005; 12/2005
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    ABSTRACT: During the first stage of a multi-year research program, BAE SYSTEMS and Ovonyx have designed, fabricated and tested a series of test chips to demonstrate full integration of a chalcogenide-based non-volatile memory element into a radiation hardened CMOS process. The test structures range from simple two- and four-point-probe material characterization macros, such as sheet resistance monitors and chalcogenide memory elements, to fully wired 64kbit memory arrays. Process integration has progressed from the previously demonstrated stand-alone chalcogenide memory elements through full memory array fabrication. Results of successful integration of the chalcogenide material used for phase-change applications in re-writable optical storage (Ge<sub>2</sub>Sb<sub>2</sub>Te<sub>5</sub>) with BAE SYSTEMS' 0.5mum radiation hardened CMOS to produce 64kbit arrays have been reported in the past. In this paper we present a description of the architecture and design of a 4Mbit, chalcogenide non-volatile memory for a 0.25mum radiation hardened CMOS process. Fabrication of the design was completed in early 2005. Electrical test results of the 4Mb chalcogenide memory hardware are presented at the conference. In addition, results from the C-RAM process transition (from BAE SYSTEMS' 0.5mum to the radiation hardened 0.25mum process) are presented
    Aerospace Conference, 2005 IEEE; 04/2005
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    ABSTRACT: The first generation of C-RAM memory is designed to greatly exceed (in density, write speed, endurance) the existing non-volatile memory solutions for space and to close the gap that exists between system requirements and availability. Based on the success of the 64 kb C-RAM program, we are designing a 4 Mb C-RAM product implemented in 0.25 μm radiation-hardened CMOS. We present a description of the architecture and design of the prototype 4 Mb chalcogenide non-volatile memory and provide schematic based simulation results showing memory operation.
    Non-Volatile Memory Technology Symposium, 2004; 12/2004
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    ABSTRACT: We report on the progress of a recent addition to non-volatile solid state memory technologies suited for space and other ionizing radiation environments. We summarize the material and processing science behind the current generation of chalcogenide phase-change memories fabricated on CMOS structures. The chalcogenide material used for phase-change applications in rewritable optical storage (Ge<sub>2</sub>Sb<sub>2</sub>Te<sub>5</sub>) has been integrated with a radiation hardened CMOS process to produce 64 kbit memory arrays. On selected arrays electrical testing demonstrated up to 100% memory cell yield, 100 ns programming and read speeds, and write currents as low as 1 mA/bit. Devices functioned normally from -55°C to 125°C. Write/read endurance has been demonstrated to 1×10<sup>8</sup> before first bit failure. Radiation results show no degradation to the hardened CMOS or effects that can be attributed to the phase-change material. Future applications of the technology are discussed.
    Aerospace Conference, 2004. Proceedings. 2004 IEEE; 04/2004
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    ABSTRACT: We report on the progress of a recent addition to non‐volatile solid state memory technologies suited for space and other ionizing radiation environments. We summarize the material and processing science behind the current generation of chalcogenide phase‐change memories fabricated on CMOS structures. The chalcogenide material used for phase‐change applications in rewritable optical storage (Ge2Sb2Te5) has been integrated with a radiation hardened CMOS process to produce 64kbit memory arrays. On selected arrays electrical testing demonstrated up to 100% memory cell yield, 100ns programming and read speeds, and write currents as low as 1mA/bit. Devices functioned normally from − 55°C to 125°C. Write/read endurance has been demonstrated to 1 × 108 before first bit failure. Radiation results show no degradation to the hardened CMOS or effects that can be attributed to the phase‐change material. Future applications of the technology are discussed. © 2004 American Institute of Physics
    02/2004; 699(1):639-649. DOI:10.1063/1.1649626
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    ABSTRACT: The chalcogenide material used for phase-change applications in rewritable optical storage (Ge<sub>2</sub>Sb<sub>2</sub>Te<sub>5</sub>) has been integrated with a 0.5-μm radiation-hardened CMOS process to produce 64-Kbit memory arrays. On selected arrays, electrical testing demonstrated up to 100% memory cell yield, 100-ns programming and read speeds, and write currents as low as 1 mA/bit. Devices functioned normally from -55°C to 125°C. Write/read endurance has been demonstrated to 1×10<sup>8</sup> before first bit failure. Total ionizing dose (TID) testing to 2 Mrad(Si) showed no degradation of chalcogenide memory element, but it identified a write current generator circuit degradation specific to the test chip, which can be easily corrected in the next generation of array and product. Static single-event effects (SEE) testing showed no effect to an effective linear energy transfer (LET<sub>EFF</sub>) of 98 MeV/mg/cm<sup>2</sup>. Dynamic SEE testing showed no latchup or single-event gate rupture (SEGR) to an LET<sub>EFF</sub> of 123 MeV/mg/cm<sup>2</sup>. Two sensitive circuits, neither containing chalcogenide elements, and both with small error cross sections, were identified. The sense amp appears sensitive to transients when reading the high-resistance state. The write driver circuit may be falsely activated during a read cycle, resulting in a reprogrammed bit. Radiation results show no degradation to the hardened CMOS or effects that can be attributed to the phase-change material.
    IEEE Transactions on Nuclear Science 01/2004; DOI:10.1109/TNS.2003.821377 · 1.46 Impact Factor
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    ABSTRACT: First Page of the Article
    Aerospace Conference, 2003. Proceedings. 2003 IEEE; 02/2003
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    ABSTRACT: BAE SYSTEMS in Manassas, Virginia, and Ovonyx, Inc., have previously reported electrical test results from stand-alone single-bit chalcogenide memories. In this paper we present a description of two test chips, one that has been used to integrate the chalcogenide memory element with BAE SYSTEMS' radiation hardened 0.5 µm CMOS technology, and another to develop 64 kbit arrays with full write-read circuitry suitable for environmental and radiation testing. Electrical test results from these test chips will be presented showing full functionality. TABLE OF CONTENTS
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    ABSTRACT: The chalcogenide material used for phase-change applications in rewritable optical storage (Ge 2 Sb 2 Te 5) has been integrated with a 0.5µm radiation hardened CMOS process to produce 64kbit memory arrays. On selected arrays electrical testing demonstrated up to 100% memory cell yield, 100ns programming and read speeds, and write currents as low as 1mA/bit. Devices functioned normally from -55°C to 125°C. Write/read endurance has been demonstrated to 1 × 10 8 before first bit failure. Total ionizing dose (TID) testing to 2Mrad(Si) showed no degradation of chalcogenide memory element. SEE testing showed no latch-up or single event gate rupture (SEGR) to an LET EFF of 123MeV/mg/cm 2 . Radiation results show no degradation to the hardened CMOS or effects that can be attributed to the phase-change material. Future applications of the technology are discussed.