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ABSTRACT: The influence of Al concentration on the current density
in GaAs-Al
c
Ga1-
c
As heterostructure is studied for two different
classes of the Generalized Thue-Morse superlattice (GTS):(i) width-barrier
GTS and(ii) height-barrier GTS. The occurrence of resonances in the
transmission is found to be highly dependent on the Al concentration as well
as on the degree of quasi-periodicity of the system. Interesting features
are noted for the current density profile with the increase in the Al
content for the width-barrier case. The use of the height-barrier GTS with
small Al content could be suggested to achieve the negative differential
conducting regimes at comparatively low applied bias. The effects of the
applied field as well as of the quasi-periodicity on the carrier
localization are also studied.
Physics of Condensed Matter 04/2012; 80(4):477-483. · 1.53 Impact Factor
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ABSTRACT: The dynamics of the complete breakup process in an Ortho Ps - He+ system
including electron loss to the continuum (ELC) is studied where both the
projectile and the target get ionized. The process is essentially a four body
problem and the present model takes account of the two centre effect on the
electron ejected from the Ps atom which is crucial for a proper description of
the ELC phenomena. The calculations are performed in the framework of Coulomb
Distorted Eikonal Approximation. The exchange effect between the target and the
projectile electron is taken into account in a consistent manner. The proper
asymptotic 3-body boundary condition for this ionization process is also
satisfied in the present model. A distinct broad ELC peak is noted in the fully
differential cross sections (5DCS) for the Ps electron corroborating
qualitatively the experiment for the Ps - He system. Both the dynamics of the
ELC from the Ps and the ejected electron from the target He+ in the FDCS are
studied using coplanar geometry. Interesting features are noted in the FDCS for
both the electrons belonging to the target and the projectile.
04/2012;
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ABSTRACT: In this paper, we analyze the effect of clock slew in subthreshold circuits. Specifically, we address the issue that variations in clock slew at the register control can cause serious timing violations. We show that clock slew variations can cause frequency targets to deviate by as much as 28% from the design goals. Based on these observations, we recognize the importance of clock slew control in subthreshold circuits. We propose a systematic approach to design the clock tree for subthreshold circuits to reduce the clock slew variations while minimizing the energy dissipation in the tree. The combined approach, including the wire sizing and dynamic nodal capacitance control, can achieve better slew control (and better timing control) at lower energy in subthreshold circuits.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 10/2011; · 1.27 Impact Factor
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ABSTRACT: The well-known asymmetric Fano resonances that results from the quantum interference between the discrete and the continuum states are noted for the first time in the ballistic transmission spectrum of the bilayer graphene tunneling structures. This unconventional tunneling transmission, in stark contrast to the monolayer graphene and to the conventional heterostructures, arises due to the quadratic dispersion of the chiral charge carriers. If the Klein tunneling (the phenomenon for normal incidence) is an unusual characteristic of the massless chiral particles, then the Fano tunneling (the phenomenon for low glancing incidence) would be the specialty for the massive chiral particles. The characteristic features of the Fano line shape are found to be highly sensitive to the direction of incidence of the charge carriers, the applied homogeneous electric field, and to the barrier height. The sharp anti-resonance at the center of the tunneling band arising due to the destructive interference between the electron and the holelike states could probably be responsible for the high negative differential conductance (NDC) in the bilayer graphene. The tunneling conductance in the double barrier structure exhibits a resonant peak with a sharp NDC region for the Fermi energy less than or equal to half of the barrier height. The present findings might have great implications in the preparation of NDC-based devices using bilayer graphene nanostructures.
Journal of Applied Physics 07/2011; 110(1):014306-014306-7. · 2.17 Impact Factor
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ABSTRACT: Research efforts to develop a novel memory technology that combines the desired traits of nonvolatility, high endurance, high speed, and low power have resulted in the emergence of spin-torque transfer RAM (STTRAM) as a promising next-generation universal memory. Although industrial efforts have been made to design efficient embedded memory arrays using STTRAM, the prospect of developing a nonvolatile field-programmable gate array (FPGA) framework with STTRAM exploiting its high integration density remains largely unexplored. In this paper, we propose a novel CMOS-STTRAM hybrid FPGA framework, identify the key design challenges, and propose optimization techniques at circuit, architecture, and application mapping levels. We show that intrinsic properties of STTRAM that distinguish it from conventional static RAM (SRAM), such as asymmetric readout power, where a cell storing “0” has 5× less read power than a cell storing “1”, can be leveraged to skew lookup table contents for FPGA power reduction. We also argue that the proposed framework should operate on static voltage-sensing-based logic evaluation. We identify static power dissipation during logic evaluation and read noise margin as key design concerns and present an optimized resistor-divider design for voltage sensing to reduce static power and noise margin. Finally, we investigate the effectiveness of Shannon-decomposition-based supply gating to reduce static power. Simulation results show improvement of 44.39% in logic area and 22.28% in delay of a configurable logic block (CLB) and average improvement of 16.1% dynamic power over a conventional CMOS FPGA design for a set of benchmark circuits.
IEEE Transactions on Nanotechnology 06/2011; · 2.29 Impact Factor
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ABSTRACT: In this paper, we analyze the energy dissipation in spin-torque-transfer random access memory array (STTRAM). We present a methodology for exploring the design space to minimize the energy dissipation of the array while maintaining required read and write quality for a given magnetic tunnel junction technology. The proposed method shows the need for proper choice of the silicon transistor width and array operating voltage to minimize the energy dissipation of the STTRAM array. The write energy is found to be 10 × greater than read energy. Hence, read-write ratio becomes a crucial factor that determines energy for STTRAM last level caches (L2). An exploration is performed across several architectural benchmarks including shared and non-shared caches for detailed energy analysis.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 06/2011; · 1.22 Impact Factor
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ABSTRACT: This paper presents a dynamically reconfigurable SRAM array for low-power mobile multimedia application. The proposed structure use a lower voltage for cells storing low-order bits and a nominal voltage for cells storing higher order bits. The architecture allows reconfigure the number of bits in the low-voltage mode to change the error characteristics of the array in run-time. Simulations in predictive 70 nm nodes show that the proposed array can obtain 45% savings in memory power with a marginal (~10%) reduction in image quality.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 02/2011; · 1.22 Impact Factor
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ABSTRACT: Increasing variations in device parameters significantly degrades the write-ability of SRAM cells in deep sub-100 nm CMOS technology. In this paper, a transient negative bit-line voltage technique is presented to improve write-ability of SRAM cell. Capacitive coupling is used to generate a transient negative voltage at the low-going bit-line during Write operation without using any on-chip or off-chip negative voltage source. Statistical simulations in a 45-nm PD/SOI technology show a 10<sup>3</sup>X reduction in the Write-failure probability with the proposed method.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 02/2011; · 1.22 Impact Factor
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ABSTRACT: Due to the high density requirement for embedded memories, such memories are highly vulnerable to process variation-induced failures. A conservative design approach can largely affect memory density and access performance. This article analyzes variation effects in SRAM and presents low-cost, adaptive postsilicon repair mechanisms.
IEEE Design and Test of Computers 01/2011; · 1.39 Impact Factor
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ABSTRACT: In this paper, a dynamic timing control technique employing a time-borrowing flip-flop with a time-borrowing detection and a clock shifter is presented to prevent timing errors of a system with a minimized performance penalty. The proposed flip-flop allows time borrowing during a time-borrowing window (TBW) on critical paths and generates a time-borrowing detection signal used by the clock shifter to stretch the clock period by TBW. This makes the system delay-error tolerant at a lower voltage or a higher frequency without any error management. To validate the proposed technique, we designed a prototype in a 180-nm CMOS technology. At a 10% activation probability of critical paths, the measurement results show a power reduction of up to 22% (at the same clock frequency) or an operating frequency increase of up to 10% (at the same power) compared to those of a conventional design.
Custom Integrated Circuits Conference (CICC), 2010 IEEE; 10/2010
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ABSTRACT: The Basketball is uniquely American game and most popular in this country and now getting popularity in worldwide. National Basketball Association(NBA)is the major basket ball league conducting basketball matches event of every year in the month of february. In a basketball match, k tickets are available and more than k people give demand for a ticket to watch the match. To earn more profit in that environment, in this paper an auction based truthful mechanism is proposed for selling all the tickets of the basketball match and it is shown that our auction based scheme is significantly better than the existing scheme in terms of the total income earned per match.
Computer Communication Control and Automation (3CA), 2010 International Symposium on; 06/2010
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ABSTRACT: This brief analyzes the circuit-induced challenges to reliability and write current scaling of spin-torque-transfer random access memory (STTRAM). We show that, at sub-90-nm nodes, increased transistor leakage increases the probability of incorrect sensing requiring a higher read current. However, a higher read current can increase the read disturb failure, particularly with a reduced write current. To satisfy the conflicting requirements of read margin and sensing accuracy, we propose a source-line biasing technique. Simulations in predictive 65-nm nodes show that the proposed solution simultaneously reduce the sensing errors and improve the read margin.
Circuits and Systems II: Express Briefs, IEEE Transactions on 04/2010; · 1.41 Impact Factor
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ABSTRACT: In nanometer scale static-RAM (SRAM) arrays, systematic inter-die and random within-die variations in process parameters can cause significant parametric failures, severely degrading parametric yield. In this paper, we investigate the interaction between the inter-die and intra-die V t variations on SRAM read and write failures. To improve the robustness of the SRAM cell, we propose a closed-loop compensation scheme using on-chip monitors that directly sense the global read stability and writability of the cell. Simulations based on 45-nm partially depleted silicon-on-insulator technology demonstrate the viability and the effectiveness of the scheme in SRAM yield enhancement.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 02/2010; · 1.22 Impact Factor
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ABSTRACT: In this paper, we investigate the combination of a novel computing paradigm referred to as Memory Based Computing (MBC) and an emerging non-volatile nanoscale memory technology, namely Spin-Torque Transfer Random Access Memory (STTRAM), to build a reconfigurable nanocomputing framework with high integration density, robustness and energy-delay efficiency. MBC uses a 2-D memory array as underlying computing element. Noting the read-dominant access pattern in MBC, we optimize the STTRAM cells to increase the energy-delay efficiency. Further, exploiting the asymmetric nature of the cells, we introduce the notion of preferential storage which optimizes the cell performance for `1' over `0' and skew the LUT content toward `1' for improved energy-delay product (EDP).
Nanotechnology, 2009. IEEE-NANO 2009. 9th IEEE Conference on; 08/2009
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ABSTRACT: In this paper, we present a new 3D wirelength distribution model which considers the contribution of through-silicon-via (TSV) on wirelength, die area, and power consumption. Since TSVs occupy the device layer together with active devices, the die area increases if TSVs are utilized. This area overhead, which in turn affects the wirelength, worsens due to the large size of TSVs themselves, which is shown to be as large as logic gates themselves. Moreover, the capacitive coupling among TSVs and wires cause non-negligible amount of parasitic capacitance, which worsens power consumption. We present and validate a new 3D wirelength distribution and power consumption model to correctly model the various impacts of TSV.
Interconnect Technology Conference, 2009. IITC 2009. IEEE International; 07/2009
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ABSTRACT: A dosimeter-on-a-chip (DoseChip) comprised of a tissue-equivalent scintillator coupled to a solid-state photomultiplier (SSPM) built using CMOS technology represents an ideal technology for a space-worthy, real-time solar-particle monitor for astronauts. It provides a tissue-equivalent response to the relevant energies and types of radiation for low-Earth orbit and interplanetary space flight to the moon or Mars. The DoseChip will complement the existing Crew Passive Dosimeters by providing real-time dosimetry and as an alarming monitor for solar particle events (SPEs). A prototype of the DoseChip was exposed to protons at three incident energies at the NASA space radiation laboratory at Brookhaven National Laboratory. The prototype provides an unambiguous, proportional response for 200, 500, and 1000 MeV protons. The measured response produced a detector response function that was used to model the behavior of an improved instrument. The data presented here indicate that a 3 times 3 times 3 mm<sup>3</sup> piece of BC-430 plastic scintillator coupled to a 2000-pixel SSPM can accommodate the needed dynamic range for protons with an incident energy of 20 MeV and greater.
Aerospace conference, 2009 IEEE; 04/2009
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ABSTRACT: In this paper we have studied the impacts of floating body effect, device leakage, and gate oxide tunneling leakage on the read and write-ability of a PD/SOI CMOS SRAM cell under Vt, L and W variations in sub-100 nm technology for the first time. The floating body effect is shown to degrade the read stability while improving the write-ability. On the other hand, the gate-to-body tunneling current improves the read stability while degrading the write-ability. It is also shown that the use of high-Vt and thick oxide cell transistors can improve leakage, read and write-ability without causing significant performance degradation. The test-chip is fabricated in sub-90 nm SOI technology to show the effectiveness of high-Vt and thick-oxide devices in improving stability of SRAM cells.
IEEE Journal of Solid-State Circuits 04/2009; · 3.23 Impact Factor
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ABSTRACT: In this paper, a profit-aware design metric is proposed to consider the overall merit of a design in terms of power and performance. A statistical design methodology is then developed to improve the economic merit of a design considering frequency binning and product price profile. A low-complexity sensitivity-based gate sizing algorithm is developed to improve economic gain of a design over its initial yield-optimized design. Finally, we present an integrated design methodology for simultaneous sizing and bin boundary determination to enhance profit under an area constraint. Experiments on a set of ISCAS'85 benchmarks show in average 19% improvement in profit for simultaneous sizing and bin boundary determination, considering both leakage power dissipation and delay bounds compared to a design initially optimized for 90% yield at iso-area in 70-nm bulk CMOS technology.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 08/2008; · 1.22 Impact Factor
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ABSTRACT: Simple ring-oscillator circuit has been used to estimate the degradation in circuit performance due to negative bias temperature instability (NBTI) effect but it fails to isolate the degradation from the NBTI for PMOS and the positive bias temperature instability (PBTI) for NMOS in high-K dielectric/metal gate CMOS technology. In this paper, we propose new circuit structures which monitor the NBTI and the PBTI effects separately while conserving the simplicity and efficiency of a ring oscillator based circuit. We also show that the proposed circuits have better sensitivity to the NBTI effect than conventional ring-oscillator circuit when they are used in technologies that experience negligible PBTI effect.
Integrated Circuit Design and Technology and Tutorial, 2008. ICICDT 2008. IEEE International Conference on; 07/2008
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ABSTRACT: Dual-threshold-voltage (V<sub>T</sub>) CMOS is an effective way to reduce leakage power in high-performance very-large-scale-integration circuits. In this paper, we explore the technology design space for dual-threshold-voltage transistor design in deep-sub-100-nm technology nodes. We propose a technique of achieving high-V<sub>T</sub> (HVT) devices using thicker gate-sidewall offset spacers to increase the channel length without increasing the printed-gate length. The effectiveness of all the dual-V<sub>T</sub> technology options-increasing channel doping, increasing gate length, and proposed technique of increasing spacer thickness-is analyzed at transistor and basic logic gate level. Results on 65-nm partially depleted silicon-on-insulator and double-gate technologies indicate that the proposed technique yields lower dynamic power consumption and lower performance penalty compared with longer gate length and high body-doping devices. Our proposed technique, however, incurs extra fabrication mask similar to achieving HVT by increasing body doping.
IEEE Transactions on Electron Devices 06/2008; · 2.32 Impact Factor
