M.K. Hudait

The Ohio State University, Columbus, OH, USA

Are you M.K. Hudait?

Claim your profile

Publications (21)32.42 Total impact

  • Source
    Conference Proceeding: Scalability study of In0.7Ga0.3As HEMTs for 22nm node and beyond logic applications
    E. Hwang, S. Mookerjea, M.K. Hudait, S. Datta
    [show abstract] [hide abstract]
    ABSTRACT: Compound semiconductor high electron mobility transistors (HEMTs) have recently gained a lot of interest for future high-speed, low-power logic applications due to their high mobility and high effective carrier velocity. Conventional Ino.7Gao.3As HEMTs with 50 to 150nm gate-length (LG) have been experimentally demonstrated with excellent device performance. In this paper, (i) we use two-dimensional numerical drift-diffusion simulations [3] to model the conventional Ino.7Gao.3As HEMTs with different LG from 15 to 200nm and investigate its scalability for future logic applications, (ii) An accurate estimation of effective mobility (μεff) and effective carrier velocity (injection) is presented, highlighting the relevance of ballistic mobility in these short-channel HEMTs. (iii) Due to degradation in performance of the conventional scaled Ino.7Gao.3As HEMT at LG=15nm, three novel HEMT device architectures are studied and the design for the ultimate scaled transistor is proposed.
    Device Research Conference (DRC), 2010; 07/2010
  • Source
    Conference Proceeding: Advanced high-K gate dielectric for high-performance short-channel In0.7Ga0.3As quantum well field effect transistors on silicon substrate for low power logic applications
    [show abstract] [hide abstract]
    ABSTRACT: This paper describes integration of an advanced composite high-K gate stack (4nm TaSiO<sub>x</sub>-2nm InP) in the In<sub>0.7</sub>Ga<sub>0.3</sub>As quantum-well field effect transistor (QWFET) on silicon substrate. The composite high-K gate stack enables both (i) thin electrical oxide thickness (t<sub>OXE</sub>) and low gate leakage (J<sub>G</sub>) and (ii) effective carrier confinement and high effective carrier velocity (V<sub>eff</sub>) in the QW channel. The L<sub>G</sub>=75nm In<sub>0.7</sub>Ga<sub>0.3</sub>As QWFET on Si with this composite high-K gate stack achieves high transconductance of 1750¿S/¿m and high drive current of 0.49mA/¿m at V<sub>DS</sub>=0.5V.
    Electron Devices Meeting (IEDM), 2009 IEEE International; 01/2010
  • Source
    Conference Proceeding: High-performance 40nm gate length InSb p-channel compressively strained quantum well field effect transistors for low-power (VCC=0.5V) logic applications
    [show abstract] [hide abstract]
    ABSTRACT: This paper describes for the first time, a high-speed and low-power III-V p-channel QWFET using a compressively strained InSb QW structure. The InSb p-channel QW device structure, grown using solid source MBE, demonstrates a high hole mobility of 1,230 cm<sup>2</sup>/V-s. The shortest 40 nm gate length (L<sub>G</sub>) transistors achieve peak transconductance (G<sub>m</sub>) of 510 muS/mum and cut-off frequency (f<sub>T</sub>) of 140 GHz at supply voltage of 0.5V. These represent the highest G<sub>m</sub> and fT ever reported for III-V p-channel FETs. In addition, effective hole velocity of this device has been measured and compared to that of the standard strained Si p-channel MOSFET.
    Electron Devices Meeting, 2008. IEDM 2008. IEEE International; 01/2009
  • Source
    Conference Proceeding: Integrating III-V on Silicon for Future Nanoelectronics
    M.K. Hudait, R. Chau
    [show abstract] [hide abstract]
    ABSTRACT: This paper describes about III-V integration on silicon and summarizes the recent progress on the research efforts to combine the merits of III-V and silicon, on the same silicon wafer, for future high-speed and low-power nanoelectronics. The successful integration of III-V on silicon can open up opportunities for integrating new functionalities and features on silicon, such as integrating logic, optoelectronic and communication platforms on the same Si wafer.
    Compound Semiconductor Integrated Circuits Symposium, 2008. CSIC '08. IEEE; 11/2008
  • Source
    Article: Carrier Transport in High-Mobility III–V Quantum-Well Transistors and Performance Impact for High-Speed Low-Power Logic Applications
    [show abstract] [hide abstract]
    ABSTRACT: DC and high-frequency device characteristics of In<sub>0.7</sub>Ga<sub>0.3</sub>As and InSb quantum-well field-effect transistors (QWFETs) are measured and benchmarked against state-of- the-art strained silicon (Si) nMOSFET devices, all measured on the same test bench. Saturation current (I<sub>on</sub>) gam of 20% is observed in the In<sub>0.7</sub>Ga<sub>0.3</sub>As QWFET over the strained Si nMOSFET at (V<sub>g</sub> - V<sub>t</sub>) = 0.3 V, V<sub>ds</sub> = 0.5 V, and matched I<sub>off</sub>, despite higher external resistance and large gate-to-channel thickness. To understand the gain in I<sub>on</sub>, the effective carrier velocities (v<sub>eff</sub>) near the source-end are extracted and it is observed that at constant (V<sub>g</sub> - V<sub>t</sub>) = 0.3 V and V<sub>ds</sub> = 0.5 V, the v<sub>eff</sub> of In<sub>0.7</sub>Ga<sub>0.3</sub>As and InSb QWFETs are 4-5times higher than that of strained silicon (Si) nMOSFETs due to the lower effective carrier mass in the QWFETs. The product of v<sub>eff</sub> and charge density (n<sub>s</sub>), which is a measure of "intrinsic" device characteristics, for the QWFETs is 50%-70% higher than strained Si at low-voltage operation despite lower ns in QWFETs. Calibrated simulations of In<sub>0.7</sub>Ga<sub>0.3</sub>As QWFETs with reduced gate-to-channel thickness and external resistance matched to the strained Si nMOSFET suggest that the higher v<sub>eff</sub> will result in more than 80% I<sub>on</sub> increase over strained Si nMOSFETs at V<sub>ds</sub> = 0.5 V, (V<sub>g</sub> - V<sub>t</sub>) = 0.3 V, and matched I<sub>off</sub>, thus showing promise for future high-speed and low-power logic applications.
    IEEE Electron Device Letters 11/2008; · 2.85 Impact Factor
  • Source
    Conference Proceeding: Heterogeneous integration of enhancement mode in0.7ga0.3as quantum well transistor on silicon substrate using thin (les 2 μm) composite buffer architecture for high-speed and low-voltage ( 0.5 v) logic applications
    [show abstract] [hide abstract]
    ABSTRACT: This paper describes for the first time, the heterogeneous integration of In<sub>0.7</sub>Ga<sub>0.3</sub>As quantum well device structure on Si substrate through a novel, thin composite metamorphic buffer architecture with the total composite buffer thickness successfully scaled down to 1.mum, resulting in high- performance short-channel enhancement-mode In<sub>0.7</sub>Ga<sub>0.3</sub>As QWFETs on Si substrate for future high-speed digital logic applications at low supply voltage such as 0.5 V.
    Electron Devices Meeting, 2007. IEDM 2007. IEEE International; 01/2008
  • Source
    Article: Ultrahigh-Speed 0.5 V Supply Voltage In0.7 Ga0.3As Quantum-Well Transistors on Silicon Substrate
    [show abstract] [hide abstract]
    ABSTRACT: The direct epitaxial growth of ultrahigh-mobility InGaAs/InAlAs quantum-well (QW) device layers onto silicon substrates using metamorphic buffer layers is demonstrated for the first time. In this letter, 80 nm physical gate length depletion-mode InGaAs QW transistors with saturated transconductance gm of 930 muS / mum and fT of 260 GHz at V<sub>DS</sub> = 0.5 V are achieved on 3.2 mum thick buffers. We expect that compound semiconductor-based advanced QW transistors could become available in the future as very high-speed and ultralow-power device technology for heterogeneous integration with the mainstream silicon CMOS.
    IEEE Electron Device Letters 09/2007; · 2.85 Impact Factor
  • Source
    Article: Carrier compensation and scattering mechanisms in Si-doped InAsyP1-y layers grown on InP substrates using intermediate InAsyP1-y step-graded buffers
    [show abstract] [hide abstract]
    ABSTRACT: Electronic transport properties of strain-relaxed Si-doped In As <sub>y</sub> P <sub>1-y</sub> layers with arsenic mole fractions between y=0.05 and y=0.50 were studied. All layers were grown on semi-insulating InP substrates by solid source molecular beam epitaxy using intermediate In As <sub>y</sub> P <sub>1-y</sub> step-graded buffers to reduce dislocation density. Variable magnetic field (0–8.5 T ) Hall effect measurements in conjunction with quantitative mobility spectrum analysis in the temperature range of 25–300 K were used to extract individual carrier mobilities, densities, and donor ionization energy as a function of temperature and alloy composition. The low field mobility is calculated by taking into account various scattering mechanisms, and these results are compared with the experimental results. At a constant electron carrier concentration of ∼2×10<sup>16</sup> cm <sup>-3</sup> , the 300 K carrier mobility increases from 2856 to 5507 cm <sup>2</sup>/ V s with increasing arsenic mole fraction from 0.05 to 0.50. The experimental mobilities are in close agreement with the theoretical results using various scattering mechanisms. Both optical polar phonon scattering and ionized impurity scattering are important at 300 K while at 100 K , ionized impurity scattering is the limiting process. Alloy scattering is found to be only of second order importance. The Si donor ionization energy was determined to be &#x223- c;2–4 meV for all alloy compositions.
    Journal of Applied Physics 10/2006; · 2.17 Impact Factor
  • Source
    Article: Direct measurement of quantum confinement effects at metal to quantum-well nanocontacts.
    C Tivarus, J P Pelz, M K Hudait, S A Ringel
    [show abstract] [hide abstract]
    ABSTRACT: Model metal-semiconductor nanostructure Schottky nanocontacts were made on cleaved heterostructures containing GaAs quantum wells (QWs) of varying width and were locally probed by ballistic electron emission microscopy. The local Schottky barrier was found to increase by approximately 0.140 eV as the QW width was systematically decreased from 15 to 1 nm, due mostly to a large (approximately 0.200 eV) quantum-confinement increase to the QW conduction band. The measured barrier increase over the full 1 to 15 nm QW range was quantitatively explained when local "interface pinning" and image force lowering effects are also considered.
    Physical Review Letters 06/2005; 94(20):206803. · 7.37 Impact Factor
  • Source
    Article: Photoconductivity decay in metamorphic InAsP/InGaAs double heterostructures grown on InAsyP1−y compositionally step-graded buffers
    [show abstract] [hide abstract]
    ABSTRACT: Lattice-mismatched InAs0.32P0.68/In0.68Ga0.32As/InAs0.32P0.68 double heterostructures (DH) were grown on compositionally graded InAsyP1−y/InP substrates by solid-source molecular-beam epitaxy (MBE) out to a misfit of ∼ 1%. The kinetics of carrier recombination were investigated in the nearly totally relaxed MBE-grown DH structures using photoconductivity decay (PCD) measurements. High minority carrier lifetimes of 4–5 μs close to the radiation limit were measured, indicating the ability of MBE-grown InAsyP1−y buffers in achieving high-electronic-quality, low-band-gap mismatched InGaAs layers. Analysis suggests that very low interface recombination velocities are achieved. A photogenerated carrier diffusion model is presented to explain the initial nonlinear decays observed in PCD data for these heterostructures.
    Applied Physics Letters 02/2005; 86(7):071908-071908-3. · 3.84 Impact Factor
  • Source
    Article: Comparison of mixed anion, InAsyP1-y and mixed cation, InxAl1-xAs metamorphic buffers grown by molecular beam epitaxy on (100) InP substrates
    [show abstract] [hide abstract]
    ABSTRACT: The structural, morphological, and defect properties of mixed anion, InAs <sub>y</sub> P <sub>1-y</sub> and mixed cation, In <sub>x</sub> Al <sub>1-x</sub> As metamorphic step-graded buffers grown on InP substrates are investigated and compared. Two types of buffers were grown to span the identical range of lattice constants and lattice mismatch (∼1.1–1.2%) on (100) InP substrates by solid source molecular beam epitaxy. Symmetric relaxation of ∼90% in the two orthogonal <110> directions with minimal lattice tilt was observed for the terminal InAs <sub>0.4</sub> P <sub>0.6</sub> and In <sub>0.7</sub> Al <sub>0.3</sub> As overlayers of each graded buffer type, indicating nearly equal numbers of α and β dislocations were formed during the relaxation process and that the relaxation is near equilibrium and hence insensitive to asymmetric dislocation kinetics. Atomic force microscopy reveals extremely ordered crosshatch morphology and very low root mean square (rms) roughness of ∼2.2 nm for the InAsP relaxed buffers compared to the InAlAs relaxed buffers (∼7.3 nm) at the same degree of lattice mismatch with respect to the InP substrates. Moreover, phase decomposition is observed for the InAlAs buffers, whereas InAsP buffers displayed ideal, step-graded buffer characteristics. The impact of the structural differences between the two buffer types on metamorphic devices was demonstrated by comparing identical 0.6 eV band gap lattice-mismatched In <sub>0.69</sub> Ga <sub>0.31</sub> As thermophotovoltaic (TPV) devices that were grown on these buffers. Clearly superior device performance was achieved on InAs <sub>y P <sub>1-y</sub> buffers, which is attributed primarily to the impact of layer roughness on the carrier recombination rates near the front window/emitter interface of the TPV devices. © 2004 American Institute of Physics.
    Journal of Applied Physics 05/2004; · 2.17 Impact Factor
  • Source
    Article: 0.6-eV bandgap In/sub 0.69/Ga/sub 0.31/As thermophotovoltaic devices grown on InAs/sub y/P/sub 1-y/ step-graded buffers by molecular beam epitaxy
    [show abstract] [hide abstract]
    ABSTRACT: Single-junction, lattice-mismatched (LMM) In/sub 0.69/Ga/sub 0.31/As thermophotovoltaic (TPV) devices with bandgaps of 0.60 eV were grown on InP substrates by solid-source molecular beam epitaxy (MBE). Step-graded InAs/sub y/P/sub 1-y/ buffer layers with a total thickness of 1.6 /spl mu/m were used to mitigate the effects of 1.1% lattice mismatch between the device layer and the InP substrate. High-performance single-junction devices were achieved, with an open-circuit voltage of 0.357 V and a fill factor of 68.1% measured at a short-circuit current density of 1.18 A/cm/sup 2/ under high-intensity, low emissivity white light illumination. Device performance uniformity was outstanding, measuring to better than 1.0% across a 2-in diameter InP wafer indicating the promise of MBE growth for large area TPV device arrays.
    IEEE Electron Device Letters 10/2003; · 2.85 Impact Factor
  • Source
    Article: High-quality InAsyP1−y step-graded buffer by molecular-beam epitaxy
    [show abstract] [hide abstract]
    ABSTRACT: Relaxed, high-quality, compositionally step-graded InAsyP1−y layers with an As composition of y = 0.4, corresponding to a lattice mismatch of ∼1.3% were grown on InP substrates using solid-source molecular-beam epitaxy. Each layer was found to be nearly fully relaxed observed by triple axis x-ray diffraction, and plan-view transmission electron microscopy revealed an average threading dislocations of 4×106 cm−2 within the InAs0.4P0.6 cap layer. Extremely ordered crosshatch morphology was observed with very low surface roughness (3.16 nm) compared to cation-based In0.7Al0.3As/InxAl1−xAs/InP graded buffers (10.53 nm) with similar mismatch and span of lattice constants on InP. The results show that InAsyP1−y graded buffers on InP are promising candidates as virtual substrates for infrared and high-speed metamorphic III–V devices. © 2003 American Institute of Physics.
    Applied Physics Letters 05/2003; 82(19):3212-3214. · 3.84 Impact Factor
  • Article: 0.6eV bandgap In0.69Ga0.31As thermophotovoltaic devices grown on InAsyP1-y step-graded buffers by molecular beam epitaxy
    [show abstract] [hide abstract]
    ABSTRACT: Single-junction, lattice-mismatched (LMM) In0.69Ga0.31As thermophotovoltaic (TPV) devices with bandgaps of 0.60 eV were grown on InP substrates by solid-source molecular beam epitaxy (MBE). Step-graded InAsyP1-y buffer layers with a total thickness of 1.6 μm were used to mitigate the effects of 1.1% lattice mismatch between the device layer and the InP substrate. High-performance single-junction devices were achieved, with an open-circuit voltage of 0.357 V and a fill factor of 68.1% measured at a short-circuit current density of 1.18 A/cm2 under high-intensity, low emissivity white light illumination. Device performance uniformity was outstanding, measuring to better than 1.0% across a 2-in diameter InP wafer indicating the promise of MBE growth for large area TPV device arrays.
    IEEE Electron Device Letters - IEEE ELECTRON DEV LETT. 01/2003; 24(9):538-540.
  • Source
    Article: High-performance In/sub 0.53/Ga/sub 0.47/As thermophotovoltaic devices grown by solid source molecular beam epitaxy
    [show abstract] [hide abstract]
    ABSTRACT: In/sub 0.53/Ga/sub 0.47/As-based monolithic interconnected modules (MIMs) of thermophotovoltaic (TPV) devices lattice-matched to InP were grown by solid source molecular beam epitaxy. The MIM device consisted of ten individual In/sub 0.53/Ga/sub 0.47/As TPV cells connected in series on an InP substrate. An open-circuit voltage (V/sub oc/) of 4.82 V, short-circuit current density (J/sub sc/) of 1.03 A/cm/sup 2/ and fill factor of /spl sim/73% were achieved for a ten-junction MIM with a bandgap of 0.74 eV under high intensity white light illumination. Device performance uniformity was better than 1.5% across a full 2-in InP wafer. The V/sub oc/ and J/sub sc/ values are the highest yet reported for 0.74-eV band gap n-p-n MIM devices.
    IEEE Electron Device Letters 01/2003; · 2.85 Impact Factor
  • Source
    Article: Doping dependence of the barrier height and ideality factor of Au/n-GaAs Schottky diodes at low temperatures
    M K Hudait, S B Krupanidhi
    [show abstract] [hide abstract]
    ABSTRACT: The barrier height and ideality factor of Au/n-GaAs Schottky diodes grown by metal-organic vapor-phase epitaxy (MOVPE) on undoped and Si-doped n-GaAs substrates were determined in the doping range of 2.5 Â 10 15 – 1 Â 10 18 cm À3 at low temperatures. The thermionic-emission zero-bias barrier height for current transport decreases rapidly at concentrations greater than 1 Â 10 18 cm À3 . The ideality factor also increases very rapidly at higher concentration and at lower temperature. The results agree quite well with thermionic field emission (TFE) theory. The doping dependence of the barrier height and the ideality factor were obtained in the concentration range of 2.5 Â 10 15 – 1.0 Â 10 18 cm À3 and the results are well described using TFE theory. An excellent match between the homogeneous barrier height and the effective barrier height was observed which supports the good quality of the GaAs film. The observed variation in the zero-bias barrier height and the ideality factor can also be explained in terms of barrier height inhomogeneities in the Schottky diode. r 2001 Elsevier Science B.V. All rights reserved.
    Physica B. 01/2001; 307:125-137.
  • Source
    Article: Anomalous current transport in Au/low-doped n-GaAs Schottky barrier diodes at low temperatures
    [show abstract] [hide abstract]
    ABSTRACT: effect, the zero-bias barrier height was found to exhibit two different trends in the temperature ranges of 77–160K and 160–300K. The variation in the flat-band barrier height with temperature was found to be -(4.7±0.2)×104eVK-1, approximately equal to that of the energy band gap. The value of the Richardson constant, A**, was found to be 0.27A cm-2K-2 after considering the temperature dependence of the barrier height. The estimated value of this constant suggested the possibility of an interfacial oxide between the metal and the semiconductor. Investigations suggested the possibility of a thermionic field-emission-dominated current transport with a higher characteristic energy than that predicted by the theory. The observed variation in the zero-bias barrier height and the ideality factor could be explained in terms of barrier height inhomogenities in the Schottky diode.
    Applied Physics A 12/1998; 68(1):49-55. · 1.63 Impact Factor
  • Source
    Conference Proceeding: Effect of V/III ratio on the optical properties of LPMOVPE grown undoped GaAs epi-films
    [show abstract] [hide abstract]
    ABSTRACT: Low temperature photoluminescence spectroscopy is used extensively to study the distribution of defects, concerning the type and impurity in a semiconductor film. Typical photoluminescence spectra are observed in a near band edge region. The undoped GaAs epitaxial layers grown by low pressure metal organic vapor phase epitaxy under different V/III ratios, an optimum ratio corresponding to a minimum number of shallow impurities was clearly identified. The V/III ratio has strong effect on the optical properties of undoped GaAs epitaxial layers. When the V/III ratio was varied from 45 to 87, the electron concentration, n, of undoped GaAs increased with increasing V/III ratio. Below the V/III ratio of 45 in our case, the sample exhibited a p-type behavior, which has been identified by photoluminescence as well as depth profiling by Electro-chemical Capacitance Voltage (ECV) profiler
    Optoelectronic and Microelectronic Materials And Devices Proceedings, 1996 Conference on; 01/1997
  • Article: Interface states density distribution in Au/n-GaAs Schottky diodes on n-Ge and n-GaAs substrates
    M.K. Hudait, S.B. Krupanidhi
    [show abstract] [hide abstract]
    ABSTRACT: The current–voltage (I–V) and capacitance–voltage (C–V) characteristics of Au/n-GaAs Schottky diodes on n-Ge substrates are investigated and compared with characteristics of diodes on GaAs substrates. The diodes show the non-ideal behavior of I–V characteristics with an ideality factor of 1.13 and barrier height of 0.735 eV. The forward bias saturation current was found to be large (3×10−10 A vs. 4.32×10−12 A) in the GaAs/Ge Schottky diodes compared with the GaAs/GaAs diodes. The energy distribution of interface states was determined from the forward bias I–V characteristics by taking into account the bias dependence of the effective barrier height, though it is small. The interface states density was found to be large in the Au/n-GaAs/n-Ge structure compared with the Au/n-GaAs/n+-GaAs structure. The possible explanation for the increase in the interface states density in the former structure was highlighted.
    Materials Science and Engineering: B.
  • Source
    Article: Low temperature photoluminescence properties of Zn-doped GaAs
    [show abstract] [hide abstract]
    ABSTRACT: Dimethylzinc (DMZn) was used as a p-type dopant in GaAs grown by low pressure metalorganic chemical vapor deposition (MOCVD). The influence of growth parameters, such as, DMZn mole fractions, growth temperature, trimethylgallium (TMGa) mole fractions, substrate surfaces on the Zn incorporation have been studied. The surface morphology of the layers was measured by scanning electron microscopy (SEM). The hole concentrations and zinc (Zn) incorporation efficiency are studied by using Hall effect, electrochemical capacitance voltage (ECV) profiler, and low temperature photoluminescence (LTPL) spectroscopy as functions of hole concentration (1017−1.5×1020 cm−3) and experimental temperatures (4.2–300 K). The hole concentration increases with increasing DMZn and TMGa mole fractions and decreases linearly with increasing growth temperature. The main PL peak shifted to lower energy and the full width at half maximum (FWHM) increased with increasing hole concentration. An empirical relation for FWHM, ΔEp, band gap, Eg, and band gap shrinkage, ΔEg in Zn doped GaAs as a function of hole concentration were obtained. These relations are considered a useful tool to determine the hole concentration in Zn doped GaAs by low temperature PL measurement. The hole concentration increases with increasing TMGa mole fraction and the main peak is shifted to lower energy side.
    Materials Science and Engineering: B.

Institutions

  • 2003–2006
    • The Ohio State University
      • • Department of Electrical and Computer Engineering
      • • Department of Physics
      Columbus, OH, USA
  • 1997
    • Central Lab Bangalore
      Bengalore, State of Karnataka, India