A.C. Scogna

Cisco Systems, Inc, San Jose, California, United States

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Publications (36)7.29 Total impact

  • [Show abstract] [Hide abstract]
    ABSTRACT: Package and PCB co-simulation is common in system level companies for the prediction of high-speed channel performance. In recent times, chip companies have been paying closer attention to package and PCB co-simulations in order to guarantee the performances of these chips at the system level. However, full-wave package and PCB co-simulation can be challenging: if the package and PCB are modeled together, the co-simulation is limited by either available computational resource, due to the extremely large memory consumption, or by affordable simulation time. The current, widely adopted method in industry, for PCB and package co-simulation, is to model them separately. There has been little investigation of where to separate/segment the PCB and package and build a reference plane. The reference plane is critical to the simulation results of the entire channel. It is recognized that a TEM wave is required at the reference plane so that the current and voltage are well defined. It can be difficult to tell if a TEM wave is established at the reference plane and if it is not, what is the solution? This paper investigates these details and will give a more general solution for PCB and package co-simulation based on the consideration of accuracy and efficiency.
    Electromagnetic Compatibility (EMC), 2013 IEEE International Symposium on; 01/2013
  • Antonio Ciccomancini Scogna, ChunTong Chiang, Linus Lau, LianKheng Teoh, HsuenYen Lee
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    ABSTRACT: The continuous demand on wide bandwidth and high-speed data rate is pushing the signal spectra to be considered in simulations at the stage of 50GHz and beyond. Data rate through backplane is developing at 15Gbps and the next generation is targeted at 25Gbps. At such high data rates with extra wide frequency spectra for signals, lots of challenges are brought into the system level simulations including affordable simulation time, computational resources and required accuracy. Time to market is critical in industry due to the market share while products are outdated very quickly. Minimum simulation time is always desired and appreciated. The minimum simulation time is related to the available computational resources, simulation tools and the requirement on accuracy. For a system with above given conditions, which are the most cases in product development in the industry, the simulation time is solely dependent on modeling methodology, which is the key in system level simulation. Package and printed circuit board (PCB) co-design is common in system analysis for the prediction of high-speed channel performance. In recent times, chip companies have been closely looking into package and PCB co-simulations in order to guarantee the performances of these chips at the system level. However, full-wave package and PCB co-simulation can be challenging: if the package and the PCB are modeled together, the co-simulation is limited by either available computational resource, due to the extremely large memory consumption, or by affordable simulation time. The current, widely adopted method in industry, for PCB and package co-simulation, is to model them separately. There has been some investigation of where to separate/segment the PCB and package and build a reference plane; however, in most of the cases, only very simple models are used to verify the proposed methods. It is known that the reference plane is critical to the simulation results of the entire channel and it is recog- ized that a transversal electromagnetic wave (TEM) wave is required at the reference plane so that the current and voltage are well defined. Unfortunately, this is sometimes challenging due to the complexity of the structure and the port definition in most of the commercial Electromagnetic (EM) tools. This paper investigates these details on a realistic test structure and gives some general solution for PCB and package system co-simulation. The model under test consists of a 10 layers PCB in standard FR4 material with εr=4.5 and tgδ=0.035 at 1GHz. The package is 8 layers flip chip technology, εr=3.32 and tgδ=0.0175 at 1GHz. Due to the complexity and the high density of the nets routing, waveguide ports cannot be used. Therefore, in order to mimic a port set up as close as possible to TEM wave propagation, a virtual reference plane is used and the port is defined by a small port source gap between the end of a bump and/or pin and the metal sheet which acts as the virtual ground plane. Results of the proposed methodology applied to the partitioned model of PCB and package are compared with the 3D EM simulation of the full model and validated with measurements up to 40GHz. Other two modeling techniques are also investigated. In the first one, the GND layers are slightly extended and the ports are located inside the ground planes. In the second one, the ports are defined at the ground plane edges and a small gap is added between the boundaries and the truncated area. Details will be provided in the presentation. Very good agreement can be observed when comparing the S-parameters of the cascaded models with the S-parameters of the full model. The proposed techniques greatly simplified the co-design process and reduce the simulation time up to 5X, therefore they can be easily extended to study the influence of the PCB effects, such as PCB via length, trace routing, and escape area definition.
    Electrical Performance of Electronic Packaging and Systems (EPEPS), 2013 IEEE 22nd Conference on; 01/2013
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    ABSTRACT: The electrical performance of vias in multilayer PCBs is investigated. In particular the resonance effect due to overlapping anti-pads is characterized and an analytical formulation based on the dimensions of the cavity formed by the anti-pads and the vias is used to predict such a resonance. A prototype board is fabricated and measured results confirm the predicted results obtained from 3D electromagnetic simulation.
    Electrical Performance of Electronic Packaging and Systems (EPEPS), 2012 IEEE 21st Conference on; 01/2012
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    ABSTRACT: Printed circuit board (PCB) design is getting critical as data rate approaching 25 Gbps (Gigabit per second) and beyond in networking systems. Channel loss, noise coupling and discontinuities are limiting the performance of high-speed channels. Equalization techniques including linear, feed forward and decision feedback are widely used in high-speed SerDes channels to compensate the channel losses. But these are still not sufficient for some extra long channels, and low loss PCB dielectric materials have to be used finally. The consequence is the cost of the networking system soaring significantly. In this paper, a hybrid stack-up is proposed for PCBs used in networking systems. Electrical performance of the hybrid stack-up is investigated in both frequency-domain and time-domain, and a positive conclusion for the hybrid stack-up is reached based on its cost and electrical performances.
    Electromagnetic Compatibility (EMC), 2012 IEEE International Symposium on; 01/2012
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    ABSTRACT: This paper presents a solution to mitigate the signal vias to power plane coupling using controlled-return-current guard traces with shorting vias. The proposed design allow to considerably suppress the noise due to uncontrolled return path of the current coupled to power planes in multilayered packages and boards, avoiding signal integrity and electromagnetic interference problems.
    Electrical Design of Advanced Packaging and Systems Symposium (EDAPS), 2012 IEEE; 01/2012
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    ABSTRACT: This paper presents the design of serial chip-to-chip communication at 20 Gbps including modeling and correlation for PCBs (Printed Circuit Boards) with FR4 substrate materials. The entire channel under investigation includes two packages, a 21-layer ceramic and a 12-layer organic, and a 22-layer PCB. A probing station, microprobes and a VNA are used to measure the entire channel S-parameters and the measurement is correlated to the simulation up to 20 GHz. Extended study for the channel with low loss PCB substrate material is simulated. Time-domain eye comparisons for the FR4 channel, low loss channel, and the FR4 channel with equalization are given. A general design rule as well as new technologies for the high-speed channel design at 20 Gbps and beyond are discussed and given in the conclusion.
    Electromagnetic Compatibility (EMC), 2010 IEEE International Symposium on; 08/2010
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    ABSTRACT: Widespread use of the Web 2.0 Internet applications such as video streaming and social networking are continuously demanding higher bandwidth network equipment. Electrical designers increasingly face more and more challenges to deliver higher speed products within short development cycle due to design complexity and new multi-GHz signal integrity problems. This paper presents a modeling and simulation methodology through chip/package/PCB (printed circuit board) co-design and co-optimization to enable a terabit per second network switch linecard design. Channel design techniques such as BGA (Ball Grid Array) pin backdrill, via tuning, and low loss interconnects are outlined. Full wave 3D modeling techniques with optimal model segmentation, model cascading and model optimization are discussed. At the end, correlation between lab measurement and simulation in both frequency and time domains are investigated.
    Electromagnetic Compatibility (EMC), 2010 IEEE International Symposium on; 08/2010
  • A.C. Scogna, A. Orlandi, V. Ricchiuti
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    ABSTRACT: In this paper, the analysis of the signal integrity and the power integrity (PI) performance of different types of electromagnetic bandgap structures (EBGs) in presence of differential (DIFF) striplines is proposed. Four different configurations of 2-D embedded EBG layers are analyzed. A test vehicle consisting in a 12-layer printed circuit board in standard FR4 material is built, and the measured results (validated by means of 3-D electromagnetic simulations) are used to estimate the signal quality in terms of the transmission parameter S<sub>21</sub>, time-domain reflectometry, and eye pattern at the terminations. The PI is, instead, analyzed by means of the noise coefficient from the source to different positions along the planes (S<sub>21</sub>). Results confirm the reliability of 2-D EBGs for noise mitigation and the enhancement in the signal quality when DIFF signals are used.
    IEEE Transactions on Electromagnetic Compatibility 06/2010; · 1.33 Impact Factor
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    ABSTRACT: The ground surface perturbation lattice (GSPL) structure is proposed to suppress parallel-plate noises by embedding metal crystals into power/ground planes. The design idea is similar to the photonic crystal power/ground layer (PCPL), consisted in high permittivity dielectric material rods embedded between power and ground layer. In contrast to the PCPL structure, the GSPL can be fabricated without employing high cost material and by using standard PCB/package manufacturing process; therefore it is more suitable for real world applications. In this study, it is discussed how the parameters of the GSPL structure influence the bandgap and how to design the GSPL in order to replace PCPL.
    Electromagnetic Compatibility (APEMC), 2010 Asia-Pacific Symposium on; 05/2010
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    A.C. Scogna, A. Orlandi
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    ABSTRACT: In this work a systematic analysis of the signal integrity performance of substrate integrated waveguide structures (SIW) is reported. It is numerically demonstrated how the transmission of very high bit rate (within the frequency range 30-80GHz) can be successfully achieved by using this type of structure and an equivalent stripline model is used as reference for the purpose. The numerical model of the SIW is validated by measured data available in literature. An extension of the single SIW structure is proposed: it consists of two adjacent single ended SIW and it is named 2-SIW. Crosstalk analysis and transmitting performance for the 2-SIW structure and a new configuration denoted inverted-U is finally carried out.
    Electromagnetic Compatibility (EMC), 2010 IEEE International Symposium on; 01/2010
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    ABSTRACT: This paper investigates the suppression of unwanted noise in high speed power buses by the adoption of photonic crystal power/ground layer (PCPL) structure. The performance of PCPL with different densities of high dielectric rods is analyzed in terms of S-parameters and electric field distribution. An attempt is made in order to relate geometrical properties (like rods' density and filling ratio) to the shift of the central frequency of the band gaps a well as bandwidth. The simulated results are validated by means of comparison with measured data.
    Electromagnetic Compatibility, 2009. EMC 2009. IEEE International Symposium on; 09/2009
  • G. Romo, A.C. Scogna
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    ABSTRACT: A high-performance substrate integrated waveguide (SIW) filter formed by top and bottom metal layers which embed a dielectric slab and two sidewalls of metallic vias is presented. Two different configurations (named as in-line and off-line) are proposed and two different design techniques are discussed: direct method and indirect method. In both cases modeled/simulated results are validated by means of measurements and good agreement is observed over the whole frequency range 0-110 GHz. The indirect method allows the prediction of the stop bands with very small computational effort; therefore it is a very promising technique for design of SIW structures.
    Signal Integrity and High-Speed Interconnects, 2009. IMWS 2009. IEEE MTT-S International Microwave Workshop Series on; 03/2009
  • A.C. Scogna
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    ABSTRACT: In this paper a two dimensional (2D) electromagnetic bandgap (EBG) structure is proposed for SSN mitigation in PWR/GND plane pairs. Excellent noise suppression (-60 dB) is achieved in multiple bands within the range 0-8 GHz with a low start frequency. Because of the 2D EBG, no additional metal layer is required. Signal integrity analysis is also studied by modelling a microstrip to stripline transition and by evaluating insertion loss and noise coefficients for both single-ended and differential signalling.
    Electrical Performance of Electronic Packaging, 2008 IEEE-EPEP; 11/2008
  • A.C. Scogna, M. Schauer
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    ABSTRACT: The present paper investigates the sensitivity of the transmission properties of a simple stripline model to the copper surface roughness. Different profiles are modeled and analyzed by means of three dimensional full wave numerical simulations. Hammerstad and Jensen analytical formulation is demonstrated to be valid only for a specific profile of surface roughness. A visual basic macro is implemented in order to model random distribution of surface roughness profiles. Numerical results show in this case similar performance of the stripline model.
    Electromagnetic Compatibility - EMC Europe, 2008 International Symposium on; 10/2008
  • A.C. Scogna
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    ABSTRACT: Aim of this paper is the signal integrity analysis of multilayer boards with emphasis on the effect of non-functional pads. In particular it is demonstrated how removing the nonfunctional pads to reduce the coupling mechanisms of the pads with the planes above and/or below can not be considered a general rule of thumb due to possible larger impedance variation (TDR). Accurate and reliable numerical simulations are in this case really important in order to correctly determine the impact of those non-functional pads on the signal integrity. A 26 layers board is analyzed by simulating with a three dimensional EM field solver a portion of the original Allegro file.
    Electromagnetic Compatibility, 2008. EMC 2008. IEEE International Symposium on; 09/2008
  • A.C. Scogna, A. Orlandi, V. Ricciuti
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    ABSTRACT: In this work the analysis of the signal and the power integrity performances of two different types of EBG structures in presence of single ended and differential striplines is proposed. The two EBG patterns have square patches and double L or meandered branches. The signal quality is measured in terms of the transmission parameter S<sub>21</sub> and the eye pattern at the terminations; the power integrity is instead analyzed by means of the noise coefficient from the source to different positions along the planes.
    Signal Propagation on Interconnects, 2008. SPI 2008. 12th IEEE Workshop on; 06/2008
  • A.C. Scogna
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    ABSTRACT: This paper describes the parallel-plate waveguide (PPW) noise mitigation by means of shorting vias and/or Virtual Island. The proposed method is already know in literature, nevertheless important considerations are here addressed: 1) the same noise mitigation level proposed in [S. Nam et. al., IEEE Trans. on Microwave Theory and Technique (2005)] can be achieved by using only shorting vias, 2) the noise mitigation is strictly related to the number of shorting vias, the position and the distance from the signal via, 3) -60 dB noise suppression is obtained when array of shorting vias is used. The mitigation level is investigated both in time domain and frequency domain. Different configurations are studied and the impact of power plane with etched slots due to Virtual Islands on the signal integrity is also analyzed by evaluating TDR and insertion loss of a single-ended microstripline passing from top to bottom layer by means of a through via.
    Electromagnetic Compatibility, 2007. EMC 2007. IEEE International Symposium on; 08/2007
  • A.C. Scogna, M. Schauer
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    ABSTRACT: The present paper investigates the sensitivity of on wafer interconnect to the Si CMOS process parameters. In particular the tapered (trapezoid) etching and the conductor surface profile (Rrms) of copper foils are numerically analyzed in order to quantify their effect on the electrical performance of a stripline structure. Line impedance, insertion loss and time signal attenuation are evaluated by means of three dimensional (3D) electromagnetic (EM) simulations. Hammerstad and Jensen analytical model is implemented and results are compared with those coming from the full 3D EM simulation model. Good agreement in the frequency range 0- 50 GHz is observed.
    Electromagnetic Compatibility, 2007. EMC 2007. IEEE International Symposium on; 08/2007
  • A.C. Scogna
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    ABSTRACT: Aim of this paper is to describe the simultaneous switching noise (SSN) mitigation by means of a novel electromagnetic band gap (EBG) structure with triangle patches and hexagonal array. The proposed EBG structure allows achieving -40 dB stop band within the frequency range 6.5-9 GHz. Parametric analysis including the radius effect of the metal plated vias, the via length and the distance between the patches is performed by means of full wave simulations, based on the Finite Integration Technique. The impact of the proposed design on the signal integrity is also investigated both in time domain (eye-diagrams and TDR) and frequency domain (S-parameters). Finally dispersion diagrams of the singular unit EBG cell are analyzed by means of eigenmode solver and periodic boundary conditions.
    Electromagnetic Compatibility, 2007. EMC 2007. IEEE International Symposium on; 08/2007
  • A.C. Scogna, G. Antonini, A. Orlandi
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    ABSTRACT: The high speed digital processing in modern electronic products has made more difficult the achievement of conformity about limits emissions. To verify the requirements of standards on these emissions the use of a metallic enclosure is often necessary: in this way the power radiated by the system is reduced. In this paper the radiated emissions and the shielding performance of a metallic rack with shielding springs are studied both by dedicated experiments and by simulations. An internal source represented by a loaded monopole antenna is used to investigate the radiated emissions at 3 meters from the box. A simplified model of the antenna is proposed in the numerical model and a good agreement over a frequency range up to 1 GHz is achieved between measured results and simulated results. Shielding Effectiveness is finally evaluated by means of two different kinds of source: 1) near field (internal source) and 2) far field (plane wave source).
    Electromagnetic Compatibility, 2007. EMC 2007. IEEE International Symposium on; 08/2007

Publication Stats

122 Citations
7.29 Total Impact Points

Institutions

  • 2010
    • Cisco Systems, Inc
      San Jose, California, United States
  • 2004
    • University of Missouri
      • Department of Electrical and Computer Engineering
      Columbia, MO, United States
    • De Montfort University
      Leiscester, England, United Kingdom
  • 2002–2004
    • Università degli Studi dell'Aquila
      • Department of Civil, Construction-Architectural and Environmental Engineering
      L’Aquila, Abruzzo, Italy