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ABSTRACT: The question in the title is relevant when considering lattice-reduction-aided MIMO detectors, which achieve the same diversity as the maximum-likelihood detector while exhibiting lower complexity. In this paper we examine if all basis updates, which account for the largest complexity contribution in the Lenstra, Lenstra, Lovasz lattice reduction algorithm, are necessary for lattice reduction in the context of MIMO detection. We first provide an abstract answer to this question in the form of an idealized experiment that demonstrates the potential for a large reduction in the number of basis updates even when spatial correlation is present. Encouraged by these results, we seek a practical answer to this question by formulating a joint lattice reduction and symbol detection algorithm based on successive interference cancellation. Experimental results of the proposed method demonstrate that on average only 10% to 25% of basis updates are necessary on average depending on the degree of spatial correlation. Therefore, the answer to the question in the title is an encouraging no.
Acoustics, Speech and Signal Processing (ICASSP), 2011 IEEE International Conference on; 06/2011 · 4.63 Impact Factor
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ABSTRACT: Commonly used speech enhancement algorithms estimate the power spectral density of the noise to be removed, or make a decision about the presence of speech in a particular frame, and estimate the clean speech based on these. Errors in a noise estimate or speech activity decision may result in undesirable artifacts, and some errors may be more damaging than others. Robust Bayesian Analysis is used to analyze the sensitivity of algorithms to errors in noise estimates and improve signal-to-noise ratio while mitigating artifacts in the enhanced speech. The findings explain why some common heuristic changes to the Wiener filter algorithm are effective. A standard Wiener algorithm is used for comparison, objective quality measures are used to quantify improvement, and insights into the underlying mechanisms of heuristic methods are offered.
Acoustics, Speech and Signal Processing (ICASSP), 2011 IEEE International Conference on; 06/2011 · 4.63 Impact Factor
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ABSTRACT: The advent of multiple-input-multiple-output (MIMO) techniques has resulted in the generation of new design problems, especially in the baseband processing task of symbol detection. Lattice reduction (LR)-aided detection techniques have emerged as a low-complexity method to achieve the same diversity as the maximum likelihood detector. In this article we explore efficient hardware realization of the complex Lenstra, Lenstra, Lovász (CLLL) LR algorithm. We accomplish this task by first developing an understanding of the complex relationship between algorithm and hardware considerations. After proposing hardware-motivated algorithm modifications, we apply this understanding to the design of a 4 × 4 CLLL processor for MIMO detection. Hardware realization results on a Xilinx XC4VLX80-12 FPGA demonstrate that the CLLL processor has a throughput of over 3.5 M channel matrices per second, outperforming previously disclosed hardware realizations. In addition, the algorithm modifications and design procedures that we propose are easily applied to larger MIMO system sizes.
Circuits and Systems I: Regular Papers, IEEE Transactions on 05/2011; · 1.97 Impact Factor
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ABSTRACT: In this paper we describe a technique that uses adaptive gain control to achieve noise suppression in speech signals. The method used to map the dynamic range of the signal is based on the human auditory perceptual model. Since the processing is based on the model of human perception, the resulting noise suppressed speech is natural sounding. The computational complexity of the proposed method is low and the mapping of the dynamic range of the signal has a low delay. Because of these properties, this method is ideal for real-time implementation.
Applications of Signal Processing to Audio and Acoustics, 2009. WASPAA '09. IEEE Workshop on; 11/2009
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ABSTRACT: Modern advances in reconfigurable technologies are allowing analog circuit designers to benefit from the computational flexibility provided by large-scale field-programmable analog arrays (FPAAs). With the component density of these devices, small analog circuits as well as larger analog systems can be synthesized and tested in a shorter time and at a lower cost compared to the full design cycle. However, automated development platforms and CAD tools for these devices are far fewer than the physical synthesis tools for their digital counterparts. One of the major reasons for this is the considerably higher impact of interconnect parasitics on circuit functionality in the analog domain; therefore, performance metrics must be monitored closely. Our goal in this paper is to present a physical synthesis framework with a generic architecture specification interface and a parasitic extractor for verification of the synthesis results. Our synthesis tool can support a wide range of FPAA architectures and our simulations can successfully predict the performance metrics.
Circuit Theory and Design, 2009. ECCTD 2009. European Conference on; 09/2009
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ABSTRACT: Modern advances in reconfigurable technologies are allowing analog circuit designers to benefit from the computational flexibility provided by large-scale field-programmable analog arrays. With the component density of these devices, small analog circuits, as well as larger analog systems, can be synthesized and tested in a shorter time and at a lower cost, compared with the full design cycle. However, automated development platforms and computer-aided design tools for these devices are far fewer than the physical synthesis tools for their digital counterparts. One of the major reasons for this is the considerably higher impact of interconnect parasitics on circuit functionality in the analog domain; therefore, performance optimization must be recognized as an indispensable step of the analog physical synthesis flow. Our goal in this brief is to present a physical synthesis framework with an optimization core and an integrated simulation environment for verification of the synthesis results. Although SPICE has been used as the simulation tool for our experiments, there is no dependency on a particular circuit simulator. Our synthesis tool currently accepts SPICE netlists as input and gives priority to user-specified metrics when optimizing the synthesized circuit performance. Experimental results demonstrate the effectiveness of our approach.
Circuits and Systems II: Express Briefs, IEEE Transactions on 08/2009; · 1.41 Impact Factor
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ABSTRACT: Motivated by the unwillingness to accept the worst-case timing constraint that synchronous logic imposes, and additionally motivated by finding a supply voltage scaling scheme for datapath circuits that is unconstrained by timing errors in memory elements, the authors have built an asynchronous datapath that is embedded seamlessly into a synchronous register file. This paper will show that not only does asynchronous arithmetic logic exhibit many characteristics that allow it to be inherently lower power, but it is significantly faster than any synchronous counterpart and is a perfect candidate technology for datapath acceleration. Further, novel circuits are presented that allow asynchronous datapath units to be embedded in a synchronous environment with little overhead while the dual-rail asynchronous encoding scheme is successfully converted with equally low overhead. The authors have built a test chip being fabricated at the time of publication. The circuits on this chip will be discussed and simulation results given showing this design to be both energy and performance efficient when compared to other known datapath designs.
Circuits and Systems, 2009. ISCAS 2009. IEEE International Symposium on; 06/2009
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ABSTRACT: Lattice reduction-aided equalization techniques have emerged as a low-complexity method to achieve the same diversity as maximum likelihood detectors. We address the VLSI implementation of these LR-aided equalizers by modifying the CLLL algorithm from a fixed-point hardware perspective. We then apply the modified algorithm together with additional micro-architecture and operation scheduling enhancements to create an updated CLLL processor. Finally, through BER simulations and FPGA synthesis results we demonstrate the suitability of our CLLL processor for integration into a 64-QAM MIMO system.
Acoustics, Speech and Signal Processing, 2009. ICASSP 2009. IEEE International Conference on; 05/2009 · 4.63 Impact Factor
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ABSTRACT: Motivated by the many stochastic processes found in biology that allow for ultra-efficient computing, this paper explores circuit implementations for stochastic computation in hardware. Several novel contributions are presented in this paper, namely a dynamically controllable system of random number generators that produces Bernoulli random variables, exponentially distributed random variables, and allows for random variables of an arbitrary distribution to be generated. This system is implemented on a reconfigurable analog chipset allowing for the first time ever a hardware stochastic process with a user input to control the probability distribution. The utility of this system is demonstrated by implementing the well-known Gillespie algorithm for simulating an arbitrary biological system trajectory of sufficiently small molecules where over a 127times performance improvement over current software approaches is shown.
Biomedical Circuits and Systems Conference, 2008. BioCAS 2008. IEEE; 12/2008
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ABSTRACT: For MIMO transmissions lattice reduction-aided equalizers have emerged as a potential low-complexity method for achieving the same receiver diversity as high-complexity maximum likelihood (ML) detectors. Toward the VLSI implementation of lattice reduction algorithms, we address the integer-rounding operation present in these algorithms. In particular we exploit the reciprocal-reuse of a complex-valued lattice reduction algorithm, the Complex Lenstra, Lenstra, Lovasz (CLLL) algorithm, by employing the reciprocation-based Newton-Raphson iteration technique. We derive an easily-computed upper-bound of the relative quotient error for a given reciprocal table size. In addition we show how the CLLL algorithm contains part of the rounding error detection operations necessary for Newton-Raphson-based methods. Application of this analysis results in an area-efficient hardware architecture for FPGAs that requires a small reciprocal look-up table. Implementation results on both Xilinx Virtex4 and Virtex5 FPGAs show that our approach exhibits slightly smaller average latency and requires 40% less equivalent gates than a comparison architecture constructed from existing IP blocks.
Circuits and Systems, 2008. MWSCAS 2008. 51st Midwest Symposium on; 09/2008
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ABSTRACT: MIMO transmissions (e.g., V-BLAST) have been widely adopted for high-rate high-performance communication systems. When the maximum likelihood (ML) or near-ML detector is employed, full receiver diversity is collected for V-BLAST systems at the cost of high complexity. Conversely, linear equalizers and successive interference cancellation equalizers have much lower complexity, but these equalizers degrade performance due to the loss of diversity. Lattice reduction (LR) techniques have been introduced to restore the diversity of low- complexity equalizers. In this paper we describe the architecture and results of the first VLSI implementation of the CLLL LR algorithm.
Circuits and Systems for Communications, 2008. ICCSC 2008. 4th IEEE International Conference on; 06/2008
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ABSTRACT: In this paper, we propose a spatially recursive optical flow estimation (OFE) framework using adaptive filtering. One of most successful OFE algorithms is a gradient-based least- squares (LS) within a local image window because of high performance and low-complexity. However, it has some redundancies for calculating successive LS among adjacent pixels. Therefore, we suggest an efficient framework using recursive least-squares (RLS) and adaptive filtering to improve the computational efficiency. The performance and computational complexity are compared to least-squares OFE and spatially recursive OFE algorithms. Based on these results, we conclude that our proposed algorithm framework under proper window size can reduce computational complexity especially as the number of motion modeling parameters increases by using the property of RLS and adaptive filtering.
Acoustics, Speech and Signal Processing, 2008. ICASSP 2008. IEEE International Conference on; 05/2008 · 4.63 Impact Factor
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ABSTRACT: A 16 x 16 programmable analog radial-basis-function (RBF) based classifier is demonstrated. The distribution of each feature is modeled by a Gaussian function, which is realized by a proposed floating-gate bump circuit having bell-shaped transfer characteristics. The maximum likelihood, mean, and variance of the distribution are stored in floating-gate transistors and are independently programmable. By cascading these floating-gate bump circuits, the overall transfer characteristics approximate a multivariate Gaussian distribution with a diagonal covariance matrix. An array of these circuits constitutes a compact RBF-based classifier. When followed by a winner-take-all circuit, the analog classifier can implement vector quantization. Automatic gender identification is implemented on a 16 x 16 analog vector quantizer chip as one possible audio application of this work. The performance of the analog classifier is comparable to that of digital counter -parts. The proposed approach can be at least two orders of magnitude more power efficient than the digital microprocessors at the same task.
Acoustics, Speech and Signal Processing, 2008. ICASSP 2008. IEEE International Conference on; 05/2008 · 4.63 Impact Factor
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ABSTRACT: In this paper, we propose a novel bandpass filter design that incorporates automatic gain control (AGC). The gain control in the filter reduces the performance requirements of a wide-band AGC, and allows for low-power multichannel compression. The filter achieves up to 15 dB of compression on a 55-dB input dynamic range and is tunable over the audio frequency range, with microwatt power consumption and <5% harmonic distortion.
Circuits and Systems I: Regular Papers, IEEE Transactions on 05/2008; · 1.97 Impact Factor
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ABSTRACT: In this paper, we propose a temporal dynamic index reordering vector quantization for wavelet-based embedded coding. Da Silva et al. introduced a vector quantization concept that is similar to EZW called a successive approximation vector quantizer (SAVQ). The successive refinement process is defined as a temporal process in our proposed algorithm. The temporal updates are performed in every refinement pass, and the updates of codevectors reflect the updates of angles for vector approximation. Because the approximation trajectory of SAVQ is similar to that of the least-mean- square algorithm, temporal redundancy does not seem to be obvious. However, the redundancy becomes more clear in the improved SAVQ. By carefully analyzing the angle transitions, we are successfully able to apply dynamic index reordering vector quantization (DIRVQ) in the temporal domain and improve the coding performance. Efficient encoding and decoding algorithms for D<sub>4</sub> lattice vector quantization are also proposed, and the algorithms can be applicable to DIRVQ to reduce the computational complexity of the reordering process. Experiments are performed with the 2x2 vector size. For almost all tested bpp's the PSNR performance of our proposed algorithm for a lena image outperforms that of SAVQ up to 0.18 dB. Improvement is measured for the highly detailed baboon image as well.
Data Compression Conference, 2008. DCC 2008; 04/2008
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ABSTRACT: A reconfigurable implementation of distributed arithmetic (DA) for post-processing applications is described. The input of DA is received in digital form and its analog coefficients are set by using the floating-gate voltage references. The effect of the offset and gain errors on DA computational accuracy is analyzed, and theoretical results for the limitations of this design strategy are presented. This architecture is fabricated in a 0.5-mum CMOS process, and configured as a 16-tap finite impulse response (FIR) filter to demonstrate the reconfigurability and computational efficiency. The measurement results for comb, low-pass, and bandpass filters at 32/50-kHz sampling frequencies are presented. This implementation occupies around 1.125 mm<sup>2</sup> of die area and consumes 16 mW of static power. The filter order can be increased at the cost of 0.011 mm<sup>2</sup> of die area and 0.02 mW of power per tap.
Circuits and Systems I: Regular Papers, IEEE Transactions on 04/2008; · 1.97 Impact Factor
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ABSTRACT: A compact analog programmable multidimensional radial basis function (RBF)-based classifier is demonstrated. The probability distribution of each feature in the templates is modeled by a Gaussian function that is approximately realized by the bell-shaped transfer characteristics of a proposed floating-gate circuit, which we term a floating-gate bump circuit. The maximum likelihood, the mean, and the variance of the distribution are stored in floating-gate transistors and are independently programmable. By cascading these floating-gate bump circuits, the overall transfer characteristics approximate a multivariate Gaussian function with a diagonal covariance matrix. An array of these circuits constitute a compact multidimensional RBF-based classifier that can easily implement a Gaussian mixture model. When followed by a winner-take-all circuit, the RBF-based classifier forms an analog vector quantizer. We use receiver operating characteristic curves and equal error rate to evaluate the performance of our RBF-based classifier as well as a resultant analog vector quantizer. We show that the classifier performance is comparable to that of digital counterparts. The proposed approach can be at least two orders of magnitude more power efficient than the digital microprocessors at the same task.
Circuits and Systems I: Regular Papers, IEEE Transactions on 11/2007; · 1.97 Impact Factor
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ABSTRACT: In this paper, we develop new mixed-mode implementations for particle Biters and compare them to a digital implementation. The motivation for the mixed-mode implementation is to achieve low-power implementation of particle filters. The specific application considered is a bearings-only, single-target tracking algorithm. Specifically, we develop mixed-mode implementations that use analog components to realize nonlinear functions in the particle filter algorithm. The analog implementation of nonlinear functions uses low-power multiple-input translinear element (MITE) networks. Simulation results for one mixed-mode implementation of the bearings-only tracker show that the analog errors are low enough to support accurate tracking. Redesign of the mixed-mode implementation in a second form with more analog components will result in nearly twenty times less power dissipation.
Communications, Computers and Signal Processing, 2007. PacRim 2007. IEEE Pacific Rim Conference on; 09/2007
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ABSTRACT: An algorithm verification methodology for cooperative analog-digital signal processing imaging system is presented, and a simulation tool for software and hardware co-verification is developed for rapid algorithm verification. Unlike traditional behavioral simulation, the behavior of the architectural structure includes the characteristics of sensor and circuit mismatch and parasitic effects so that algorithm-level simulation can predict the performance of a true physical system. A case study of gradient- based optical flow estimation algorithm is demonstrated.
Circuits and Systems, 2007. MWSCAS 2007. 50th Midwest Symposium on; 09/2007
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ABSTRACT: We present a system Verilog/C code creation and compilation system that creates a ModelSim-Matlab shared memory interface optimized for the input/output specification of the user Verilog or VHDL. We describe how our interface approach is an improvement over the commercially available Mathworks Link for ModelSim, which requires the user to complete Verilog or VHDL data type conversion using slow m-files and to write interrupt-driven callback functions. Our interface approach frees the user from data type conversion and has the user write sequential test scripts but also takes advantage of a delayed-simulation execution technique to reduce simulation time. We demonstrate the utility of our interface approach by comparing a test script for a pipeline FFT processor to the corresponding Link for ModelSim version.
Circuits and Systems, 2007. MWSCAS 2007. 50th Midwest Symposium on; 09/2007
