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ABSTRACT: A simple and unified fundamental theory on the mechanism of stress memorization technique (SMT) is presented for the first time. This theory is based on the difference in thermal properties of the materials involved in SMT process, i.e., silicon (channel), polysilicon (gate), amorphous silicon (source/drain), SiO<sub>2</sub> (gate oxide), as well as Si<sub>3</sub>N<sub>4</sub> (SMT nitride stressor layer), which lead to deformations during thermal anneal and SMT. This theory accounts for all the results published to date in SMT and provides important physical insights. As a demonstration of predictive capability of this theory, a 45-nm process was modified using a novel anneal sequence which raises the stress in the channel. The experimental data after the change yield additional 5% performance boost for NFET compared to a baseline SMT process.
IEEE Electron Device Letters 05/2011; · 2.85 Impact Factor
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ABSTRACT: For the first time, short channel effects (SCE) of the nFET has been improved while achieving a performance boost of 7% (additive to the process induced stress technique). This was achieved by realizing a steep halo profile via strategically positioned carbon regions at the source and drain extension (SDE) regions. The tailored halo profiles also decreased the overlap (C<sub>ov</sub>) and junction capacitance (Cj). In effect, a resultant 6.5% decrease in ring oscillator (RO) delay was obtained. The carbon co- implanted device has indicated no compromise in the reliability and noise performance.
VLSI Technology, Systems and Applications, 2008. VLSI-TSA 2008. International Symposium on; 05/2008
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S.S. Tan,
S Fang,
J Yuan,
L Zhao,
Y M Lee,
J J Kim,
R Robinson,
J Yan,
J Park,
M. Belyansky, [......],
S D Kim,
N. Rovedo,
H Shang,
H. Ng,
Y Li,
J. Sudijono,
E. Quek, S. Chu,
R. Divakaruni,
S. Iyer
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ABSTRACT: A novel low cost technique to improve device performance by enhanced stress proximity technique (eSPT) with recessed S/D (ReSD) has been demonstrated for the first time. pFET performance improvement of 40% was demonstrated with eSPT. pFET performance with Ion of 520 uA/um at Ioff of InA/um was achieved with the low cost processes. With optimized eSPT, 15% improvement in ring delay has been demonstrated.
VLSI Technology, Systems and Applications, 2008. VLSI-TSA 2008. International Symposium on; 05/2008
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ABSTRACT: In this paper, modeling and predictive simulations of advanced junction formation for CMOS devices based on atomistic kinetic Monte Carlo (kMC) process simulator are presented. First, we will briefly discuss the different challenges and alternatives for the formation of advanced ultra-shallow junctions for the forthcoming generation of CMOS devices. We will present the physical atomistic modeling used in term of damage evolution, dopant diffusion and clustering, interaction with interfaces and the impact of impurities, which are crucial for accurate simulations. Subsequently, comparisons with a wide range of SIMS, sheet resistance measurement as well as electrical device characteristics showed that experimental results were remarkably well reproduced by the simulations. Finally, we shall demonstrate that device optimization can be achieved based on kMC process simulations, even for novel co- implant processes. This paves the way for the use of kMC in the design of devices and the optimization of junction formation to improve device performance.
Junction Technology, 2007 International Workshop on; 07/2007
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B. Colombeau,
K.R.C. Mok,
S.H. Yeong,
F. Benistant,
B. Indajang,
O. Tan,
B. Yang,
Y. Li,
M. Jaraiz,
N.E.B. Cowern, S. Chu
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ABSTRACT: For the first time, this work shows that the design and optimization of nanoCMOS devices can be achieved from atomistic physics-based process modeling. Remarkable prediction of device characteristics can be obtained even for novel co-implant processes. This extends the strength of TCAD in manufacturing for future generations of nanoCMOS devices.
Electron Devices Meeting, 2006. IEDM '06. International; 01/2007
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Solid-State Device Research Conference, 2002. Proceeding of the 32nd European; 10/2002
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ABSTRACT: An additional NLDD Rapid Thermal Annealing (RTA) had been implemented in thin-gate and thick-gate NMOS transistors. The threshold voltage (Vt) distribution at different gate lengths was investigated for devices with and without NLDD RTA. Lower roll-up and roll-off of Vt was observed with the inclusion of NLDD RTA. However, this observation only occurred for phosphorus-LDD NMOS devices rather than arsenic-LDD NMOS devices. Based on experimental results, TCAD tools was applied to analyze the removal of implant-induced damages by LDD RTA and to investigate the difference in channel profiles before and after LDD RTA. Finally, the mechanism of less Reverse Short Channel Effect and Short Channel Effect with LDD RTA was presented through TCAD simulation results.
Advanced Semiconductor Manufacturing Conference and Workshop, 2003 IEEEI/SEMI;
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ABSTRACT: Carbon co-implant is well known to suppress boron transient enhanced diffusion (TED) in silicon. The modeling of carbon-interstitial clusters (CICs) has been extensively studied and is now widely used in Technology Computer Aided Design (TCAD). It has already been reported in literature that carbon implant in the channel of NMOS transistor is highly effective for the suppression of oxidation-enhanced diffusion (OED) of boron while leading to poor boron activation. In order to account for this deactivation, we need to consider that the active boron equilibrium concentration is modified by the presence of carbon in non-amorphized silicon region with high concentration of interstitials. In this paper, for the first time, we show the effective TCAD modeling of boron deactivation in the presence of carbon in a NMOS transistor. The model is based on boron–carbon-interstitial clusters formed in the non-amorphized silicon region, thereby reducing active boron concentration. The model can be applied to accurately predict variations of threshold voltage as a function of channel length for NMOS devices with carbon implanted into the channel or halo regions. The tool used in this work is a commercial simulator based on the continuum approach.
Solid-State Electronics.
