Publications (11)8.26 Total impact
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Article: Nanocrystal Memory Cell Integration in a Stand-Alone 16-Mb nor Flash Device
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ABSTRACT: We report on the full process integration of nanocrystal (NC) memory cells in a stand-alone 16-Mb NOR Flash device. The Si NCs are deposited by chemical vapor deposition on a thin tunnel oxide, whose surface is treated with a low thermal budget process, which increases NC density and minimizes oxide degradation. The device fabrication has been obtained by means of conventional Flash technology, which is integrated with the CMOS periphery with high- and low-voltage transistors and charge pump capacitors. The memory program and erase threshold voltage distributions are well separated and narrow. The voltage distribution widths are related to NC sizes and dispersion, and bigger NCs can induce a cell reliability weakness. An endurance issue is also related to the use of an oxide/nitride/oxide dielectric which acts as a charge trapping layer, causing a shift in the program/erase window and a distribution broadening during cycling.IEEE Transactions on Electron Devices 07/2007; · 2.32 Impact Factor -
Article: Performance and reliability features of advanced nonvolatile memories based on discrete traps (silicon nanocrystals, SONOS)
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ABSTRACT: In this paper, an overview of today's status and progress, as well as tomorrow's challenges and trends, in the field of advanced nonvolatile memories based on discrete traps is given. In particular, unique features of silicon nanocrystal and SONOS memories will be illustrated through original recent data. The main potentials and main issues of these technologies as candidates to push further the scaling limits of conventional floating-gate Flash devices will be evaluated.IEEE Transactions on Device and Materials Reliability 10/2004; · 1.54 Impact Factor -
Conference Proceeding: How far will silicon nanocrystals push the scaling limits of NVMs technologies?
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ABSTRACT: For the first time, memory devices with optimized high density (2E12#/cm<sup>2</sup>) LPCVD Si nanocrystals have been reproducibly achieved and studied on an extensive statistical basis (from single cell up to 1 Mb test-array) under different programming conditions. An original experimental and theoretical analysis of the threshold voltage shift distribution shows that Si nanocrystals have serious potential to push the scaling of NOR and NAND flash at least to the 35 nm and 65 nm nodes, respectively.Electron Devices Meeting, 2003. IEDM '03 Technical Digest. IEEE International; 01/2004 -
Article: Peculiar aspects of nanocrystal memory cells: data and extrapolations
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ABSTRACT: Nanocrystal memory cell are a promising candidate for the scaling of nonvolatile memories in which the conventional floating gate is replaced by an array of nanocrystals. The aim of this paper is to present the results of a thorough investigation of the possibilities and the limitations of such new memory cell. In particular, we focus on devices characterized by a very thin tunnel oxide layer and by silicon nanocrystals formed by chemical vapor deposition. The direct tunneling of the electrons through the tunnel oxide, their storage into the silicon nanocrystals, and furthermore, retention, endurance, and drain turn-on effects, well-known issues for nonvolatile memories, are all investigated. The cell can be also programmed by channel hot electron injection, allowing the possibility to multibit storage. The suppression of the drain turn-on and the possibility of using this cell for multibit storage give us a clear evidence of the distributed nature of the charge storage.IEEE Transactions on Nanotechnology 01/2004; · 2.29 Impact Factor -
Conference Proceeding: Localized charge storage in nanocrystal memories: feasibility of a multi-bit cell
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ABSTRACT: We have realized Si nanocrystal memory cells in which the Si dots have been deposited by chemical vapor deposition (CVD) on the tunnel oxide and then covered by a CVD control oxide. In this paper we report a study on the potential of this type of cell for multi-bit storage. In particular, the possibilities offered by these devices from the point of view of program/erase mechanisms, endurance, and charge retention are shown and discussed.European Solid-State Device Research, 2003 33rd Conference on. ESSDERC '03; 10/2003 -
Article: Charging effects in Si quantum dots for Non Volatile Memories applications monitored by Electrostatic Force Microscopy
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ABSTRACT: Nanoscale structures have been recently proposed as charge storage nodes due to their potential applications for future nanoscale memory devices. Our approach is based on the idea of using Si nanodots as discrete floating gates. To experimentally investigate such potential, we have fabricated MOS structures with Si nanocrystals. The dots have been deposited onto an ultra-thin tunnel oxide by chemical vapour deposition, and then annealed at 1000 °C for 40 s, to crystallize all the dots. After deposition the dots have been covered by a CVD SiO2 layer, thus resulting in dots completely embedded in stoichiometric silicon oxide. The nanocrystal density and size have been studied by energy filtered TEM (EFTEM) analysis. An electrostatic force microscope has been used to locally inject the charge. By applying a relatively large tip voltage a few dots have been charged, and the shift in the tip phase has been monitored. The shift in the phase is attributed to the presence of the charge in the sample. A comparison between n and p type samples is also shown.MRS Proceedings. 12/2002; 794. -
Conference Proceeding: Reliability and Retention Study of Nanocrystal Cell Array
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ABSTRACT: Not AvailableSolid-State Device Research Conference, 2002. Proceeding of the 32nd European; 10/2002 -
Article: Nanocrystal MOS memories obtained by LPCVD deposition of Si nanograins
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ABSTRACT: We have realized silicon quantum dots embedded in SiO2 which act as nano-floating gates of MOS memories. The dots with nanometer sizes have been deposited by LPCVD on a 3nm tunnel oxide. Two processes at a fixed pressure have been explored by varying the temperature. SiH4 with a N2 carrier gas have been used in the former case, SiH4 and H2 have been used in the latter. In both cases a nanocrystalline silicon layer is obtained, with nanocrystals a density higher than 1011 cm-2. The process with H2 carrier gas is more controllable and leads to the formation of nanocrystals with a more regular shape. In both cases the density of grains is able to originate detectable threshold shifts in the memory cell, even though process SiH4 and H2 shows better electrical performances.Diffusion and Defect Data Pt.B: Solid State Phenomena. 01/2002; 82-84:663-668. -
Article: Exclusion zone surrounding silicon nanoclusters formed by rapid thermal chemical vapour deposition on SiO2
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ABSTRACT: We present results of an experimental investigation on the nearest-neighbour distance of silicon nanoclusters obtained by chemical vapour deposition of silane on silicon oxide substrates. Structural characterization has been performed by means of energy filtered transmission electron microscopy, which allowed us to observe dot sizes down to 0.5 nm in radius. We have found that silicon nanodots after deposition are separated by a minimum distance of about 4 nm. This effect has also been observed on samples deposited in the same conditions on substrates which have been subjected to different chemical treatments. The phenomenon is attributed to the existence of a capture zone, within which new deposited Si monomers preferentially contribute to the growth of a previously nucleated seed rather than aggregate to form a new nucleus. As a confirmation of this hypothesis, the average dot radius has been observed to be proportional to the capture region size, thus indicating a scaling behaviour for this process. Moreover when the inter-dot distance distribution is scaled to its average value, it collapses into a universal curve.Surface Science. -
Article: Reliability and retention study of nanocrystal cell arrays
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ABSTRACT: We have studied nanocrystal memory arrays with 2.56 × 10 5 cells (256kb) in which Si nanocrystals have been obtained by CVD deposition on a 4nm tunnel oxide. The cells in the array are programmed and erased by electron tunneling through the SiO 2 dielectric. We find that the threshold voltage distribution has little spread. In addition the arrays are also very robust with respect to drain stress and show good retention. -
Article: Observation of the nucleation kinetics of Si quantum dots on SiO2 by energy filtered transmission electron microscopy
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ABSTRACT: The formation of Si quantum dots on SiO2 by chemical vapour deposition of SiH4 is investigated by energy filtered transmission electron microscopy. It is demonstrated that this technique allows to measure size distributions down to dimensions of about 1 nm. This capability allows to put in evidence some important microscopic features of the nucleation process, whose consideration is fundamental to control the Si dot size. These aspects are shown and discussed.Applied Surface Science 205:304-308. · 2.10 Impact Factor
