G. Ammendola

National Research Council, Roma, Latium, Italy

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Publications (21)19.18 Total impact

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    ABSTRACT: We report on the full process integration of nanocrystal (NC) memory cells in a stand-alone 16-Mb NOR Flash device. The Si NCs are deposited by chemical vapor deposition on a thin tunnel oxide, whose surface is treated with a low thermal budget process, which increases NC density and minimizes oxide degradation. The device fabrication has been obtained by means of conventional Flash technology, which is integrated with the CMOS periphery with high- and low-voltage transistors and charge pump capacitors. The memory program and erase threshold voltage distributions are well separated and narrow. The voltage distribution widths are related to NC sizes and dispersion, and bigger NCs can induce a cell reliability weakness. An endurance issue is also related to the use of an oxide/nitride/oxide dielectric which acts as a charge trapping layer, causing a shift in the program/erase window and a distribution broadening during cycling.
    IEEE Transactions on Electron Devices 07/2007; DOI:10.1109/TED.2007.895868 · 2.36 Impact Factor
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    ABSTRACT: The formation of Si dots by chemical vapor deposition is studied from the very early stages of the dot formation up to about 25% of substrate coverage. Structural characterization is mainly performed by means of energy filtered transmission electron microscopy, which couples chemical information to very high spatial resolution. The dots are shown to be surrounded by Si-free regions and this is attributed to the Si adatom capture mechanism from each nucleus. The data are discussed in the framework of a self-similar model, which takes into account the dot local environment, the adatom diffusion and the continuous nucleation of new islands. From the fit to the data the correlation between the dot size and the capture area is obtained and the number of deactivated nucleation sites is quantified.
    Physical Review B 03/2005; 71(12):5322. DOI:10.1103/PhysRevB.71.125322 · 3.66 Impact Factor
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    ABSTRACT: In this paper, an overview of today's status and progress, as well as tomorrow's challenges and trends, in the field of advanced nonvolatile memories based on discrete traps is given. In particular, unique features of silicon nanocrystal and SONOS memories will be illustrated through original recent data. The main potentials and main issues of these technologies as candidates to push further the scaling limits of conventional floating-gate Flash devices will be evaluated.
    IEEE Transactions on Device and Materials Reliability 10/2004; DOI:10.1109/TDMR.2004.837209 · 1.54 Impact Factor
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    ABSTRACT: We present a complete study of Si nanocrystals growth by Chemical Vapor Deposition. Si NCs are grown using SiH4 as precursor, on thermal SiO2, deposited Si3N4 and Al2O3. We have studied the influence of the experimental parameters on Si-NCs formation. On SiO2 and Al2O3, we have identified OH groups as nucleation sites2. Hence, by controlling the OH density on the SiO2 surface, we can monitor the Si-QDs density between 1010 and 1.5 × 1012/cm2. To control the Si-QDs size, we have developed an original two steps process which separates the nucleation and the growth of Si-QDs. In the first step, the density is fixed by exposing the treated SiO2 surface to SiH4 precursor. In the second step, the Si-QDs growth is obtained only on previously formed Si nuclei by using a selective precursor, namely SiH2Cl2.
    Solid-State Electronics 09/2004; 48(9):1503–1509. DOI:10.1016/j.sse.2004.03.015 · 1.51 Impact Factor
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    ABSTRACT: We have realized Si nanocrystal memory cells in which the Si dots have been deposited by CVD on SiO2 and then covered by a CVD control oxide. In this paper, we report a study on the potential of these cells for dual bit storage.
    Microelectronic Engineering 04/2004; 72(1):411-414. DOI:10.1016/j.mee.2004.01.023 · 1.34 Impact Factor
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    ABSTRACT: A study was conducted on the nucleation process of Si quantum dots deposited by rapid thermal chemical vapor deposition (CVD) of SiH4 with H2 as carrier gas on thermally oxidized silicon substrates in the range of temperatures between 500 and 600°C. It was found that for silane fluxes equal to 400 sccm, and temperatures lower than 575°C, the deposition rate was in the regime limited by surface reaction rate. In this range of experimental conditions it was possible to follow the dot nucleation and growth kinetics.
    02/2004; 95(4-4):2049-2055. DOI:10.1063/1.1639950
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    ABSTRACT: We present results of an experimental investigation on the nearest-neighbour distance of silicon nanoclusters obtained by chemical vapour deposition of silane on silicon oxide substrates. Structural characterization has been performed by means of energy filtered transmission electron microscopy, which allowed us to observe dot sizes down to 0.5 nm in radius. We have found that silicon nanodots after deposition are separated by a minimum distance of about 4 nm. This effect has also been observed on samples deposited in the same conditions on substrates which have been subjected to different chemical treatments. The phenomenon is attributed to the existence of a capture zone, within which new deposited Si monomers preferentially contribute to the growth of a previously nucleated seed rather than aggregate to form a new nucleus. As a confirmation of this hypothesis, the average dot radius has been observed to be proportional to the capture region size, thus indicating a scaling behaviour for this process. Moreover when the inter-dot distance distribution is scaled to its average value, it collapses into a universal curve.
    Surface Science 02/2004; 550:119-126. DOI:10.1016/j.susc.2003.12.026 · 1.87 Impact Factor
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    ABSTRACT: For the first time, memory devices with optimized high density (2E12#/cm<sup>2</sup>) LPCVD Si nanocrystals have been reproducibly achieved and studied on an extensive statistical basis (from single cell up to 1 Mb test-array) under different programming conditions. An original experimental and theoretical analysis of the threshold voltage shift distribution shows that Si nanocrystals have serious potential to push the scaling of NOR and NAND flash at least to the 35 nm and 65 nm nodes, respectively.
    Electron Devices Meeting, 2003. IEDM '03 Technical Digest. IEEE International; 01/2004
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    ABSTRACT: The formation of Si quantum dots on SiO2 by chemical vapour deposition of SiH4 is investigated in the range from the sub-monolayer to the complete coverage with Si. Energy filtered transmission electron microscopy is used to measure the dot size distributions. It is shown that this technique allows the measurement of size distributions down to dimensions of about 1nm. This capability allows the determination of some important microscopic features of the nucleation process, the consideration of which is fundamental to control the Si dot size.
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    ABSTRACT: Nanocrystal memory cell are a promising candidate for the scaling of nonvolatile memories in which the conventional floating gate is replaced by an array of nanocrystals. The aim of this paper is to present the results of a thorough investigation of the possibilities and the limitations of such new memory cell. In particular, we focus on devices characterized by a very thin tunnel oxide layer and by silicon nanocrystals formed by chemical vapor deposition. The direct tunneling of the electrons through the tunnel oxide, their storage into the silicon nanocrystals, and furthermore, retention, endurance, and drain turn-on effects, well-known issues for nonvolatile memories, are all investigated. The cell can be also programmed by channel hot electron injection, allowing the possibility to multibit storage. The suppression of the drain turn-on and the possibility of using this cell for multibit storage give us a clear evidence of the distributed nature of the charge storage.
    IEEE Transactions on Nanotechnology 01/2004; DOI:10.1109/TNANO.2003.820515 · 1.62 Impact Factor
  • 20th IEEE Non-Volatile Semiconductor Memory Workshop; 01/2004
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    ABSTRACT: Nanoscale structures have been recently proposed as charge storage nodes due to their potential applications for future nanoscale memory devices. Our approach is based on the idea of using Si nanodots as discrete floating gates. To experimentally investigate such potential, we have fabricated MOS structures with Si nanocrystals. The dots have been deposited onto an ultra-thin tunnel oxide by chemical vapor deposition (CVD) of SiH4, and then annealed at 1000 °C for 40 s, to crystallize all the dots. After deposition, the dots have been covered by a CVD SiO2 layer, thus resulting completely embedded into stoichiometric silicon oxide. The nanocrystal density and size have been studied by energy filtered TEM (EFTEM) analysis. An electrostatic force microscope has been used to locally inject and image charge. By applying a relatively large tip voltage and reducing the tip to sample separation down to the contact with the surface sample, a few dots have been charged, by appearing as protrusions on the surface. The charged dots have been monitored for up to 30 min, by showing no discharge effects either vertically, through the double barrier of oxide layers, or laterally, via cross talk effect between other close dots. © 2003 Elsevier B.V. All rights reserved.
    12/2003; 23(6-8):1047-1051. DOI:10.1016/j.msec.2003.09.162
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    ABSTRACT: Nanocrystal memories represent a promising candidate for the scaling of FLASH memories. In these devices, the charge is not stored in a continuous floating gate but in a discontinuous layer composed by numerous discrete silicon quantum dots well separated one from the other.The nanocrystals of radius of few nanometers are realized by chemical vapor deposition (CVD) of silicon on the tunnel oxide of 2.8 nm of thickness. These islands have been coated with a control oxide of 7 nm formed by CVD and incorporated in Metal-Oxide-Semiconductor structure. The devices are programmed and erased by tunnelling using low voltages and fast times. In addition, the programming can be easily achieved also by channel hot electron injection (CHEI). Furthermore, such nanocrystal memory cells have been extensively characterized in order to study the possibility to achieve dual bit operation. In fact, during channel hot electron programming, the charge can be selectively injected only at the drain-side of the cell. This remains there localized due to the presence of the SiO2 between the grains which limits the lateral charge flow. The asymmetric charge distribution represents the key concept to the multi-bit storage. In this work, we show experimental evidence of such asymmetry.
    Materials Science and Engineering C 12/2003; 23(6):687-689. DOI:10.1016/j.msec.2003.09.111 · 2.74 Impact Factor
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    ABSTRACT: We have realized Si nanocrystal memory cells in which the Si dots have been deposited by chemical vapor deposition (CVD) on the tunnel oxide and then covered by a CVD control oxide. In this paper we report a study on the potential of this type of cell for multi-bit storage. In particular, the possibilities offered by these devices from the point of view of program/erase mechanisms, endurance, and charge retention are shown and discussed.
    European Solid-State Device Research, 2003 33rd Conference on. ESSDERC '03; 10/2003
  • IEEE - Non Volatile Semiconductor Memory Workshop 2003, Monterey (CA, USA); 02/2003
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    ABSTRACT: The formation of Si quantum dots on SiO2 by chemical vapour deposition of SiH4 is investigated by energy filtered transmission electron microscopy. It is demonstrated that this technique allows to measure size distributions down to dimensions of about 1 nm. This capability allows to put in evidence some important microscopic features of the nucleation process, whose consideration is fundamental to control the Si dot size. These aspects are shown and discussed.
    Applied Surface Science 01/2003; 205(1-4):304-308. DOI:10.1016/S0169-4332(02)01155-8 · 2.54 Impact Factor
  • Proceedings of the 2003 Silicon Nanoelectronics Workshop, Kyoto, Japan; 01/2003
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    ABSTRACT: Nanoscale structures have been recently proposed as charge storage nodes due to their potential applications for future nanoscale memory devices. Our approach is based on the idea of using Si nanodots as discrete floating gates. To experimentally investigate such potential, we have fabricated MOS structures with Si nanocrystals. The dots have been deposited onto an ultra-thin tunnel oxide by chemical vapour deposition, and then annealed at 1000 °C for 40 s, to crystallize all the dots. After deposition the dots have been covered by a CVD SiO2 layer, thus resulting in dots completely embedded in stoichiometric silicon oxide. The nanocrystal density and size have been studied by energy filtered TEM (EFTEM) analysis. An electrostatic force microscope has been used to locally inject the charge. By applying a relatively large tip voltage a few dots have been charged, and the shift in the tip phase has been monitored. The shift in the phase is attributed to the presence of the charge in the sample. A comparison between n and p type samples is also shown.
    MRS Online Proceeding Library 12/2002; 794. DOI:10.1557/PROC-794-T3.43
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    ABSTRACT: Not Available
    Solid-State Device Research Conference, 2002. Proceeding of the 32nd European; 10/2002
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    ABSTRACT: We have realized silicon quantum dots embedded in SiO2 which act as nano-floating gates of MOS memories. The dots with nanometer sizes have been deposited by LPCVD on a 3nm tunnel oxide. Two processes at a fixed pressure have been explored by varying the temperature. SiH4 with a N2 carrier gas have been used in the former case, SiH4 and H2 have been used in the latter. In both cases a nanocrystalline silicon layer is obtained, with nanocrystals a density higher than 1011 cm-2. The process with H2 carrier gas is more controllable and leads to the formation of nanocrystals with a more regular shape. In both cases the density of grains is able to originate detectable threshold shifts in the memory cell, even though process SiH4 and H2 shows better electrical performances.
    01/2002; 82-84:663-668. DOI:10.4028/www.scientific.net/SSP.82-84.663