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P. De Dobbelaere, B. Analui,
E. Balmater,
D. Guckenberger,
M. Harrison,
R. Koumans,
D. Kucharski,
Y. Liang,
G. Masini,
A. Mekis, [......],
V. Sadagopan,
S. Sahni,
T.J. Sleboda,
Y. Wang,
B. Welch,
J. Witzens,
J. Yao,
S. Abdalla,
S. Gloeckner,
G. Capellini
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ABSTRACT: For the first time we demonstrate a fully self-contained photonic transceiver system on a single die with monolithically integrated Ge photo-detectors. The transceiver allows error-free bidirectional 4times10 Gb/s WDM transmission using a single CMOS die at each end of the link.
Optical Communication, 2008. ECOC 2008. 34th European Conference on; 10/2008
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T. Pinguet, B. Analui,
E. Balmater,
D. Guckenberger,
M. Harrison,
R. Koumans,
D. Kucharski,
Y. Liang,
G. Masini,
A. Mekis, [......],
T.J. Sleboda,
D. Song,
Y. Wang,
B. Welch,
J. Witzens,
J. Yao,
S. Abdalla,
S. Gloeckner,
P. De Dobbelaere,
G. Capellini
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ABSTRACT: We demonstrate monolithically integrated 4times10 Gb/s WDM transceivers built in a production 130 nm SOI CMOS process. Only light sources are external to the chip. 40 Gb/s error-free, bidirectional transmission is demonstrated.
Group IV Photonics, 2008 5th IEEE International Conference on; 10/2008
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A. Narasimha, B. Analui,
E. Balmater,
A. Clark,
T. Gal,
D. Guckenberger,
S. Gutierrez,
M. Harrison,
R. Ingram,
R. Koumans, [......],
D. Rines,
V. Sadagopan,
T.J. Sleboda,
Dan Song,
Yanxin Wang,
B. Welch,
J. Witzens,
S. Abdalla,
S. Gloeckner,
P. De Dobbelaere
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ABSTRACT: We have demonstrated a 40-Gb/s optoelectronic transceiver in a quad small form-factor pluggable (QSFP) module. Each module includes a 4xlO-Gb/s, 0.13 μm CMOS silicon-on-insulator integrated optoelectronic transceiver chip co-packaged with a single, externally modulated CW laser.
Optical Fiber communication/National Fiber Optic Engineers Conference, 2008. OFC/NFOEC 2008. Conference on; 03/2008
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A. Narasimha, B. Analui,
Y. Liang,
T.J. Sleboda,
S. Abdalla,
E. Balmater,
S. Gloeckner,
D. Guckenberger,
M. Harrison,
R.G.M.P. Koumans,
D. Kucharski,
A. Mekis,
S. Mirsaidi,
Dan Song,
T. Pinguet
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ABSTRACT: Optical and electronic building blocks required for DWDM transceivers have been integrated in a 0.13 mum CMOS SOI technology. Using these building blocks, a 4 x 10-Gb/s single-chip DWDM optoelectronic transceiver with 200 GHz channel spacing has been demonstrated. The DWDM transceiver demonstrates an unprecedented level of optoelectronic system integration, bringing all required optical and electronic transceiver functions together on a single SOI substrate. An aggregate data rate of 40 Gb/s was achieved over a single fiber, with a BER of less than 10<sup>-12</sup> and a power consumption of 3.5 W.
IEEE Journal of Solid-State Circuits 01/2008; · 3.23 Impact Factor
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ABSTRACT: We present the world's first optical transmitter monolithically integrated in a CMOS process, achieving 10 Gb/s data modulation rate at 1550 nm with an extinction ratio greater than 6 dB.
Group IV Photonics, 2007 4th IEEE International Conference on; 10/2007
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ABSTRACT: A 4-wavelength DWDM optoelectronic transceiver, implemented in a 0.13mum CMOS SOI process, achieves an aggregate rate of 40Gb/s transmission over single fiber. The four channel WDM chip, operating all four Txs and Rxs in WDM configuration consumes -3.5W. This is at nominal operating conditions.
Solid-State Circuits Conference, 2007. ISSCC 2007. Digest of Technical Papers. IEEE International; 03/2007
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ABSTRACT: A dual-channel 10 Gb/s per channel single-chip optoelectronic transceiver has been demonstrated in a 0.13-mum CMOS SOI technology. The transceiver integrates conventionally discrete optoelectronic functions such as high-speed 10-Gb/s electro-optic modulation and 10-Gb/s optical reception on an SOI substrate using a standard CMOS process. The high optical index contrast between silicon (n=3.5) and its oxide (n=1.5) allows for very large scale integration of optical devices, while the use of a standard CMOS process allows these devices to be seamlessly fabricated together with electronics on the same substrate. Such a high level of optoelectronic integration is unprecedented, and serves to substantially reduce system footprint and power dissipation, allowing efficient scaling to higher data rates and broader functionality. This paper describes the photonic components, electronic blocks, and architecture of a CMOS photonic transceiver that achieves an aggregate data rate of 20Gb/s in a dual-channel package, with a BER of less than 10<sup>-15</sup> and a power consumption of 1.25 W per channel with both channels operating simultaneously
IEEE Journal of Solid-State Circuits 01/2007; · 3.23 Impact Factor
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ABSTRACT: An eye-opening monitor (EOM) architecture that can capture a two-dimensional (2-D) map of the eye diagram of a high-speed data signal has been developed. Two single-quadrant phase rotators and one digital-to-analog converter (DAC) are used to generate rectangular masks with variable sizes and aspect ratios. Each mask is overlapped with the received eye diagram and the number of signal transitions inside the mask is recorded as error. The combination of rectangular masks with the same error creates error contours that overall provide a 2-D map of the eye. The authors have implemented a prototype circuit in 0.13-μm standard CMOS technology that operates up to 12.5 Gb/s at 1.2-V supply. The EOM maps the input eye to a 2-D error diagram with up to 68-dB mask error dynamic range. The left and right halves of the eyes are monitored separately to capture horizontally asymmetric eyes. The chip consumes 330 mW and operates reliably with supply voltages as low as 1 V at 10 Gb/s. The authors also present a detailed analysis that verifies if the measurements are in good agreement with the expected results.
IEEE Journal of Solid-State Circuits 01/2006; · 3.23 Impact Factor
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ABSTRACT: We present a method for predicting data-dependent jitter (DDJ) introduced by a general linear time-invariant LTI system based on the system's unit step response. We express the exact DDJ of a first-order system and verify the validity of the solution experimentally. We then propose a perturbation technique to generalize the analytical expression for DDJ. We highlight the significance of the unit step response in characterizing DDJ and emphasize that bandwidth is not a complete measure for predicting DDJ. We separate the individual jitter contributions of prior bits and use the result to predict the DDJ of a general LTI system. In particular, we identify a dominant prior bit that signifies the well-known distribution of deterministic jitter, the two impulse functions. We also show a jitter minimization property of high-order LTI systems. We verify our generalized analytical expression of DDJ for several real systems including an integrated CMOS 10-Gb/s trans-impedance amplifier by comparing the theory and measurement results. The theory predicts the jitter with as low as only 7.5% error.
IEEE Transactions on Microwave Theory and Techniques 12/2005; · 1.85 Impact Factor
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ABSTRACT: An alternative architecture for instantaneous data recovery for burst-mode communication is introduced. The architecture can perform 1: $n$ demultiplexing without additional clock recovery phase-locked loop or sampling blocks. A finite-state machine (FSM) is formed with combinational logic and analog LC transmission line delay cells in a feedback loop. The FSM responds to input data transitions instantaneously and sets the outputs. The system reduces unit interval jitter by a factor of $n$ . The new architecture is demonstrated via a SiGe 1:2 clockless demultiplexer circuit that operates at 7.5 Gb/s.
Circuits and Systems II: Express Briefs, IEEE Transactions on 09/2005; · 1.41 Impact Factor
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ABSTRACT: We present a method for estimating data dependent jitter (DDJ) introduced by a general LTI system, based on the system's step response. A perturbation technique is used to generalize the analytical expression for DDJ. Different scales of DDJ are defined that characterize the probability distribution of jitter. In particular, we identify a dominant prior bit that signifies the well-known distribution of DDJ, the two impulse functions. We also highlight that system bandwidth is not a complete measure for predicting DDJ. We verify our generalized analytical expression of DDJ experimentally and show that estimation errors are less than 7.5%.
Microwave Symposium Digest, 2005 IEEE MTT-S International; 07/2005
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ABSTRACT: An eye-opening monitor circuit in 0.13 μm CMOS operates from 1 to 12.5Gbit/s at 1.2V supply. It maps the input eye to a 2D error diagram with 68dB mask error dynamic range. Left and right halt of the eye are monitored separately to capture asymmetric eyes. Tested input amplitude is from 50 to 400mV. The chip consumes 330mW and works at 10Gb/s with a supply voltage as low as 1V.
Solid-State Circuits Conference, 2005. Digest of Technical Papers. ISSCC. 2005 IEEE International; 03/2005
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ABSTRACT: An analysis for calculating data-dependent jitter (DDJ) in a first-order system is introduced. The predicted DDJ features unique threshold crossing times with self-similar geometry. An approximation for DDJ in second-order systems is described in terms of the damping factor and natural frequency. Higher order responses demonstrate conditions under which unique threshold crossing times do not exist and total jitter is minimized. The DDJ predictions are verified with jitter measurements in a bandwidth-limited amplifier. The predictions for both first and second-order systems anticipate the features of the observed jitter.
Circuits and Systems II: Express Briefs, IEEE Transactions on 10/2004; · 1.41 Impact Factor
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ABSTRACT: A technique for bandwidth enhancement of a given amplifier is presented. Adding several interstage passive matching networks enables the control of transfer function and frequency response behavior. Parasitic capacitances of cascaded gain stages are isolated from each other and absorbed into passive networks. A simplified design procedure, using well-known low-pass filter component values, is introduced. To demonstrate the feasibility of the method, a CMOS transimpedance amplifier (TIA) is implemented in a 0.18-μm BiCMOS technology. It achieves 3 dB bandwidth of 9.2 GHz in the presence of a 0.5-pF photodiode capacitance. This corresponds to a bandwidth enhancement ratio of 2.4 over the amplifier without the additional passive networks. The transresistance gain is 54 dBΩ, while drawing 55 mA from a 2.5-V supply. The input sensitivity of the TIA is -18 dBm for a bit error rate of 10<sup>-12</sup>.
IEEE Journal of Solid-State Circuits 09/2004; · 3.23 Impact Factor
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ABSTRACT: This paper resolves the jitter impairment of non-return-to-zero data in transmission lines. The limited bandwidth of the transmission line introduces data-dependent jitter. Crosstalk between neighbouring lines results in bounded uncorrelated jitter in the data eye. An analytical approach to representing data-dependent jitter and crosstalk-induced bounded uncorrelated jitter is presented. Comparison with jitter measurements of microstrip lines on FR4 board demonstrated accuracy to within 15% of the predictions for deterministic jitter.
Microwave Symposium Digest, 2004 IEEE MTT-S International; 07/2004
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ABSTRACT: The statistical properties of integrated passive LC delay lines are investigated. A new variation using spiral inductors and vertical parallel plate (VPP) capacitors is introduced, whose delay is primarily determined by the lateral dimensions, resulting in very accurate and repeatable delays. An MIM-based version of this line is also fabricated for comparison. Additionally, LC delay-based oscillators are implemented to compare the variations in active and passive delay elements. Experimental data is obtained from measurement of 27 and 47 sites on two wafers from two different process runs, respectively. The measurements show 0.6% delay variations for VPP-based delay line compared to 1.0% for its MIM-based counterpart.
Custom Integrated Circuits Conference, 2003. Proceedings of the IEEE 2003; 10/2003
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[show abstract]
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ABSTRACT: A new technique for bandwidth enhancement of amplifiers is developed. Adding several passive networks, which can be designed independently, enables the control of transfer function and frequency response behavior. Parasitic capacitances of cascaded gain stages are isolated from each other and absorbed into passive networks. A simplified design procedure, using well-known filter component values is introduced. To demonstrate the feasibility of the method, a CMOS trans-impedance amplifier is implemented in 0.18µm BiCMOS technology. It achieves 9.2GHz bandwidth in the presence of 0.5pF photo diode capacitance and a trans-resistance gain of 54dBΩ, while drawing 55mA from a 2.5V supply.
Solid-State Circuits Conference, 2002. ESSCIRC 2002. Proceedings of the 28th European; 10/2002
