Yan Zhang

University of California, Santa Cruz, Santa Cruz, California, United States

Are you Yan Zhang?

Claim your profile

Publications (29)19.42 Total impact

  • Source
    [Show abstract] [Hide abstract]
    ABSTRACT: The fabrication and characterization of SiGeC cantilever microcoolers are described. Silicon on insulator (SOI) was used as the substrate, and two layers of 3 µm p-SiGe 0.07 C 0.0075 and 1.14 µm n-SiGe 0.07 C 0.0075 lattice matched to silicon were grown using molecular beam epitaxy. The uni couple cooler was fabricated using conventional integrated circuit (IC) processing, and the cantilever structure was finally formed by removing the backside Si of SOI substrate by deep reactive ion etching. Devices with different n-and p-side length ratios were characterized. Cooling by 1.2K has been measured at room temperature. Modeling showed that the device performance was dominated by the smaller cooling temperature of the p-SiGeC leg of the cantilever structure. Parasitic heat conduction through the Si buffer layer is the main limitation to the device performance.
    MRS Online Proceeding Library 01/2011;
  • Source
    [Show abstract] [Hide abstract]
    ABSTRACT: We present experimental and theoretical characterization of InP-based heterostructure integrated thermionic (HIT) coolers. In particular, the effect of doping on overall device performance is characterized. Several thin-film cooler devices have been fabricated and analyzed. The coolers consist of a 1µm thick superlattice structure composed of 25 periods of InGaAs well and InGaAsP (λgap ≈ 1.3µm) barrier layers 10 and 30nm thick, respectively. The superlattice is surrounded by highly-doped InGaAs layers that serve as the cathode and anode. All layers are lattice-matched to the n-type InP substrate. N-type doping of the well layers varies from 1.5×1018cm-3 to 8×1018cm-3 between devices, while the barrier layers are undoped. Device cooling performance was measured at room-temperature. Device current-versus-voltage relationships were measured from 45K to room-temperature. Detailed models of electron transport in superlattice structures were used to simulate device performance. Experimental results indicate that low-temperature electron transport is a strong function of well layer doping and that maximum cooling will decrease as this doping is increased. Theoretical models of both I-V curves and maximum cooling agree well with experimental results. The findings indicate that low-temperature electron transport is useful to characterize potential barriers and energy filtering in HIT coolers.
    MRS Online Proceeding Library 01/2011; 793.
  • [Show abstract] [Hide abstract]
    ABSTRACT: In this paper, we describe how to use Si/SiGe superlattice microcoolers to cool the target hot spots and how a trench structure could enhance its cooling performance. The microcooler chip is gold fusion bonded with a 65 mum-thick silicon chip, where heaters are fabricated on the opposite of fusion bonding layer to simulate the hot spots. Our 3-D electrothermal simulations showed that with a trench structure, the maximum cooling and cooling power density could be doubled at hot spot region. Our experimental prototype also demonstrated a maximum cooling of ~ 2degC reduction at hot spot or a maximum cooling power density of 110 W/cm with trench structure as compared with the 0.8degC cooling without trench structure. This two-chip bonded configuration will allow the integration of spot coolers and ICs without impact on microelectronics processing process. It could be a potential on-chip hot spot cooling solution.
    IEEE Transactions on Components and Packaging Technologies 10/2008; · 0.94 Impact Factor
  • [Show abstract] [Hide abstract]
    ABSTRACT: We characterize cross-plane and in-plane Seebeck coefficients for ErAs:InGaAs/InGaAlAs superlattices with different carrier concentrations using test patterns integrated with microheaters. The microheater creates a local temperature difference, and the cross-plane Seebeck coefficients of the superlattices are determined by a combination of experimental measurements and finite element simulations. The cross-plane Seebeck coefficients are compared to the in-plane Seebeck coefficients and a significant increase in the cross-plane Seebeck coefficient over the in-plane Seebeck coefficient is observed. Differences between cross-plane and in-plane Seebeck coefficients decrease as the carrier concentration increases, which is indicative of heterostructure thermionic emission in the cross-plane direction.
    Journal of Applied Physics 02/2007; 101(3):034502-034502-5. · 2.21 Impact Factor
  • [Show abstract] [Hide abstract]
    ABSTRACT: We have studied experimentally and theoretically the cross-plane Seebeck coefficient of short period InGaAs∕InAlAs superlattices with doping concentrations ranging from 2×1018 up to 3×1019 cm−3. Measurements are performed with integrated thin film heaters in a wide temperature range of 10–300 K. It was interesting to find out that contrary to the behavior in bulk material the Seebeck coefficient did not decrease monotonically with the doping concentration. We did not observe a sign change in the Seebeck coefficient at dopings where the Fermi energy is just above a miniband. This is a sign that electrons’ lateral momentum is conserved in the transport perpendicular to superlattice layers. A preliminary theory of thermoelectric transport in superlattices in the regime of miniband formation has been developed to fit the experimental results.
    Physical review. B, Condensed matter 11/2006; 74(19). · 3.66 Impact Factor
  • Source
    Yan Zhang, Gehong Zeng, A. Shakouri
    [Show abstract] [Hide abstract]
    ABSTRACT: We fabricated a silicon microrefrigerator on a 500-mum-thick substrate with the standard integrated circuit (IC) fabrication process. The cooler achieves a maximum cooling of 1degC below ambient at room temperature. Simulations show that the cooling power density for a 40times40 mum<sup>2</sup> device exceeds 500W/cm<sup>2</sup>. The unique three-dimensional (3-D) geometry, current and heat spreading, different from conventional one-dimensional (1-D) thermoelectric device, contribute to this large cooling power density. A 3-D finite element electrothermal model is used to analyze non-ideal factors inside the device and predict its limits. The simulation results show that in the ideal situation, with low contact resistance, bulk silicon with 3-D geometry could cool ~20degC with a cooling power density of 1000W/cm <sup>2</sup> despite the low thermoelectric figure-of-merit (ZT) of the material. The large cooling power density is due to the geometry dependent heat and current spreading in the device. The non-uniformity of current and Joule heating inside the substrate also contributes to the maximum cooling of silicon microrefrigerator, exceeding 30% limit given in one-dimensional thermoelectric theory DeltaT<sub>max</sub>=0.5ZT<sub>c</sub> <sup>2</sup>, where T<sub>c</sub> is the cold side temperature. These devices can be used to remove hot spots on a chip
    IEEE Transactions on Components and Packaging Technologies 10/2006; · 0.94 Impact Factor
  • Source
    [Show abstract] [Hide abstract]
    ABSTRACT: In this paper, we addressed heating problems in integrated circuits (ICs) and proposed a thin-film thermionic cooling solution using Si/SiGe superlattice microrefrigerators. We compared our technology with the current most common solution, thermoelectric coolers, by strengthening the advantages of its compatible fabrication process as ICs for easy integration, small footprint in the order of ~ 100times100 mum<sup>2</sup>, high cooling power density, 600W/cm<sup>2</sup> and fast transient response less than 40 mus. The thermoreflectance imaging also demonstrated its localized cooling. All these features combined together to make these microrefrigerators a very promising application for on-chip temperature control, removing hot spots inside IC
    IEEE Transactions on Components and Packaging Technologies 07/2006; · 0.94 Impact Factor
  • Source
    [Show abstract] [Hide abstract]
    ABSTRACT: We designed and fabricated a three-dimensional (3D) silicon microrefrigerator, which demonstrates a cooling power density over 200W/cm with only ~1degC cooling. The high cooling power density is mainly due to the high thermal conductivity and heat spreading effects. These devices have potential application in hot-spots management to reduce the chip peak temperature and realize on chip thermal management. A finite element model is developed to study and optimize these 3D devices. The simulation results showed that the optimized doping concentration to achieve the maximum cooling for these 3D silicon microrefrigerators (5e18 cm<sup>-3</sup>) is different from the conventional ID device, where S<sup>2</sup>sigma achieves the maximum at the doping of 5e19 cm<sup>-3</sup>. At its optimized doping concentration, these silicon microrefrigerators could reach a maximum cooling of 3degC. Further studies prove that this deviation is due to the nonidea factors inherent within the device, e.g. semiconductor-metal contact resistance, Joule-heating from probe contact resistance etc. Thus to optimize the real device, it is necessary to chose a full model considering all the nonideal factors
    Semiconductor Thermal Measurement and Management Symposium, 2006 IEEE Twenty-Second Annual IEEE; 04/2006
  • Source
    [Show abstract] [Hide abstract]
    ABSTRACT: We report a wafer scale approach for the fabrication of thin-film power generators composed of arrays of 400 p and n type ErAs:InGaAs/InGaAlAs superlattice thermoelectric elements. The elements incorporate ErAs metallic nanoparticles into the semiconductor superlattice structure to provide charge carriers and create scattering centers for phonons. p- and n-type ErAs:InGaAs/InGaAlAs superlattices with a total thickness of 5 μm were grown on InP substrate using molecular beam epitaxy. The cross-plane Seebeck coefficients and cross-plane thermal conductivity of the superlattice were measured using test pattern devices and the 3ω method, respectively. Four hundred element power generators were fabricated from these 5 μm thick, 200 μm×200 μm in area superlattice elements. The output power was over 0.7 mW for an external resistor of 100 Ω with a 30 K temperature difference drop across the generator. We discuss the limitations to the generator performance and provide suggestions for improvements.
    Applied Physics Letters 03/2006; 88(11):113502-113502-3. · 3.52 Impact Factor
  • Source
    [Show abstract] [Hide abstract]
    ABSTRACT: We studied heat transfer along a silicon nanowire suspended between two thin-film heaters using a thermoreflectance imaging technique. The thermoreflectance imaging system achieved submicrometer spatial resolution and 0.1°C temperature resolution using visible light. The temperature difference across the nanowire was measured, and then its thermal resistance was calculated. Knowing the dimension of the nanowire (115 nm in width and 3.9 μm in length), we calculated the thermal conductivity of the sample, which is 46 W/mK. Thermal conductivity decreases with decreasing wire size. For a 115-nm-wide silicon nanowire, the thermal conductivity is only one-third of the bulk value. In addition, the transient response of the thin-film heaters was also examined using three-dimensional thermal models by the ANSYS program. The simulated thermal map matches well with the experimental thermoreflectance results.
    IEEE Transactions on Nanotechnology 02/2006; · 1.80 Impact Factor
  • Source
    [Show abstract] [Hide abstract]
    ABSTRACT: A three-dimensional (3-D) electrothermal model was developed to study the InP-based thin-film In<sub>0.53</sub>Ga<sub>0.47</sub>As/In<sub>0.52</sub>Al<sub>0.48</sub>As superlattice (SL) microrefrigerators for various device sizes, ranging from 40×40 to 120×120μm <sup>2</sup>. We discussed both the maximum cooling and cooling power densities (CPDs) for experimental devices, analyzed their nonidealities, and proposed an optimized structure. The simulation results demonstrated that the experimental devices with an optimized structure can achieve a maximum cooling of 3°C, or equivalently, a CPD over 300W/cm<sup>2</sup>. Furthermore, we found it was possible to achieve a maximum cooling of over 10°C; equivalently, a CPD over 900W/cm<sup>2</sup>, when the figure of merit (ZT) of InGaAs/InAlAs SL was enhanced five times with nonconserved lateral momentum structures. Besides monolithic growth, we also proposed a fusion bonding scheme to simply bond the microrefrigerator chip on the back of the hot spots, defined as two-chip integration model in this paper. The cooling effect of this model was analyzed using ANSYS simulations.
    IEEE Transactions on Components and Packaging Technologies 01/2006; · 0.94 Impact Factor
  • Source
    [Show abstract] [Hide abstract]
    ABSTRACT: Thin-film thermoelectric materials offer great potential for improving the thermoelectric figure of merit ZT due to the freedom of tailoring the electron and heat transport. The characterization of these thin films is difficult because of the coexistence of the substrate, non-ideal contact, and asymmetric three-dimensional device structure. We have investigated theoretically and experimentally the transient Harman method for measuring the ZT of a thin film Si/SiGe superlattices on a silicon substrate. 3D electrothermal simulations allow us to identify the contribution of the thin film and the substrate to the transient response. On the measurement side, ringing at short times and noise can be significantly improved by using high-speed packages and electrical impedance matching. The Joule heating contribution to the thermoelectric EMF is separated from the Peltier one by the bipolar measurement. The parasitic non-ideal effects of contacts and substrate can be removed by variable thickness superlattice method.
    Thermoelectrics, 2005. ICT 2005. 24th International Conference on; 07/2005
  • Source
    Yan Zhang, Zhixi Bian, A. Shakouri
    [Show abstract] [Hide abstract]
    ABSTRACT: In this paper, we investigate the effect of the thermoelectric leg geometry and boundary conditions on the overall device cooling performance. We present a detailed 3D electrothermal analysis of heat and current distribution in a Bi<sub>2</sub>Te<sub>3</sub> single-leg element with 50×50 μm<sup>2</sup> cold side contact area, which is smaller than the element cross section (410×410 μm<sup>2</sup>). We compared the cases when a uniform voltage is applied at the contact and when a uniform current density is applied. The finite element calculation results demonstrate that in the latter case the 3D single-leg element has a very non-uniform temperature distribution at the contact area. Maximum cooling in the center region is 92°C, which is 20% higher than the 1D limit (76°C) for a typical Bi<sub>2</sub>Te<sub>3</sub> material with ZT∼1. Calculations show that it is possible to take away 600 W/cm<sup>2</sup> at the center 20×20 μm<sup>2</sup> region, which is 6 times better than the 1D device with the same thickness. In contrast, with a boundary condition of uniform voltage at the cold side contact area, the temperature distribution is as uniform as 1D device and reaches the same maximum cooling temperature as 1D. We also propose the possibility of using array contact structures to achieve the uniform current boundary condition that can improve the maximum device cooling performance. These findings add contact geometry as another degree of freedom to engineer the performance of single and multi stage TE devices.
    Thermoelectrics, 2005. ICT 2005. 24th International Conference on; 07/2005
  • Source
    [Show abstract] [Hide abstract]
    ABSTRACT: InGaAs with embedded ErAs nano-particles is a promising material for thermoelectric applications. The incorporation of erbium arsenide metallic nanoparticles into the semiconductor can provide both charge carriers and create scattering centers for phonons. Electron filtering by heterostructure barriers can also enhance Seebeck coefficient by selective emission of hot electrons. 2.1 μm-thick ErAs/InGaAs superlattices with a period of 10 nm InAlGaAs and 20 nm InGaAs were grown using molecular beam epitaxy, and the effective doping is from 2×10<sup>18</sup> to 1×10<sup>19</sup> cm<sup>-3</sup>. Special device patterns were developed for the measurement of the cross-plane Seebeck coefficient of the superlattice layers. Using these device patterns, the combined Seebeck coefficient of superlattice and the substrate were measured and the temperature drops through the superlattice and InP substrate were determined with 3D ANSYS® simulations. The Seebeck coefficient of the superlattice layers is obtained based on the measurements and simulation results.
    Thermoelectrics, 2005. ICT 2005. 24th International Conference on; 07/2005
  • Source
    [Show abstract] [Hide abstract]
    ABSTRACT: SiGe is one of the best thermoelectric materials for high temperature applications. Superlattice structures can further enhance the thermoelectric properties by reducing the thermal conductivity and by increasing the Seebeck coefficient via selective emission of hot electrons through thermionic emission. SiGe/Si superlattice structures were grown on a silicon wafer using molecular beam epitaxy. A single element SiGe/Si superlattice thermoelectric power generator was fabricated and characterized. The device element, a 3 μm thick SiGe/Si superlattice on a 3.95 μm SiGe buffer layer, was grown on 5 inch diameter 650 microns thick silicon substrate. Output power of 0.1 W/cm with a resistive load was measured with a temperature drop of 220°C across the generator element. There was a significant parasitic lead resistance. Simulations show that if the temperature drop is increased to 300°C, a power density of 1 W/cm can be achieved when working in impedance matching condition.
    Thermoelectrics, 2005. ICT 2005. 24th International Conference on; 07/2005
  • Source
    A. Shakouri, Yan Zhang
    [Show abstract] [Hide abstract]
    ABSTRACT: An overview of recent advances in solid-state cooling utilizing thin-film silicon germanium-based microrefrigerators is given. Key parameters affecting micro cooler performance are described. A 3-μm thick 200× (3 nm Si/12 nm Si<sub>0.75</sub>Ge<sub>0.25</sub>) superlattice device can achieve maximum cooling of 4°C at room temperature, maximum cooling power density of 600 W/cm<sup>2</sup> for 40-μm diameter device and fast transient response on the order of tens of micro-seconds independent of the device size. Three-dimensional electrothermal simulations show that individual microrefrigerators could be used to remove hot spots in silicon chips with minimal increase in the overall power dissipation.
    IEEE Transactions on Components and Packaging Technologies 04/2005; · 0.94 Impact Factor
  • [Show abstract] [Hide abstract]
    ABSTRACT: In this paper we describe the experimental results of Si/SiGe superlattice microcoolers, which are used to cool the target hot spot on a 65μm-thick silicon substrate. The device areas under test range from 50×50 to 150×150 μm2 . We measured the cooling temperature at the hot spot region versus the current supplied to the microcooler, as well as the thermal resistance, and the cooling power density (CPD, also defined as heat flux — the flow of heat per unit area in W/cm2 ) of these devices. The experimental results show the maximum cooling at the hot spot region approaches 1°C for device area 150×150μm2 at 80°C, and CPD up to ∼110W/cm2 for device area 50×50×2 μm2 (two 50×50μm2 device array, as illustrated in Figure 3) at 80°C. The two-chip bonded configuration will allow the integration of spot coolers and integrated circuit chips with minimum impact on the processing of microelectronic devices. Key parameters limiting the cooling performance at the hot spots are also discussed.
    ASME 2005 Pacific Rim Technical Conference and Exhibition on Integration and Packaging of MEMS, NEMS, and Electronic Systems collocated with the ASME 2005 Heat Transfer Summer Conference; 01/2005
  • [Show abstract] [Hide abstract]
    ABSTRACT: Driven by shrinking feature sizes, microprocessor “hot-spots” — with their associated high heat flux and sharp temperature gradients — have emerged as the primary “driver” for on-chip thermal management of today’s IC technology. Solid state thermoelectric micro-coolers offer great promise for reducing the severity of on-chip “hot-spots”, but the theoretical cooling potential of these devices, fabricated on the back of the silicon die in an IC package, has yet to be determined. The results of a three-dimensional electro-thermal finite-element modeling study of such a micro-cooler are presented. Attention is focused on the hot-spot temperature reductions associated with variations in micro-cooler geometry, chip thickness, and chip doping concentration, along with the parasitic Joule heating effects from the electrical contact resistance and current flow through the silicon. The modeling results help to define the optimum solid-state cooling configuration and reveal that, for the conditions examined, nearly 80% of the hot-spot temperature rise of 2.5°C can be removed from a 70μm × 70μm, 680W/cm2 hot-spot on a 50μm thick silicon die with a single micro-cooler.
    ASME 2005 Pacific Rim Technical Conference and Exhibition on Integration and Packaging of MEMS, NEMS, and Electronic Systems collocated with the ASME 2005 Heat Transfer Summer Conference; 01/2005
  • Source
    [Show abstract] [Hide abstract]
    ABSTRACT: We report the fabrication and characterization of thin film power generators composed 400 p- and n-type ErAs:InGaAs/InGaAlAs superlattice thermoelectric elements. The thermoelectric elements incorporate erbium arsenide metallic nanoparticles into the semiconductor superlattice structure to provide charge carriers and create scattering centers for phonons. 10 µm p- and n-type InGaAs/InGaAlAs superlattices with embedded ErAs nano-particles were grown on InP substrates using molecular beam epitaxy. Thermal conductivity values were measured using the 3ω method and cross-plane Seebeck coefficients were determined using Seebeck device test patterns. 400 element ErAs:InGaAs/InGaAlAs thin film power generators were fabricated from superlattice elements 10 µm thick and 200 µm × 200 µm in area. The output power was 4.7 milliwatts for an external electrical load resistor of 150 Ω at about 80 K temperature difference drop across the generator. We discuss the limitations to the generator's performance and provide suggestions for further improvement.
    MRS Proceedings. 12/2004; 886.
  • Source
    [Show abstract] [Hide abstract]
    ABSTRACT: Modeling and optimization of bulk SiGe thin-film coolers are described. Thin-film coolers can provide large cooling power densities compared to commercial thermoelectrics. Thin-film SiGe coolers have been demonstrated with maximum cooling of 4°C at room temperature and with cooling power density exceeding 500 W/cm 2 . Important parameters in the design of such coolers are investigated theoretically and are compared with experimental data. Thermoelectric cooling, joule heating, and heat conduction are included in the model as well as non-ideal effects such as contact resistance, geometrical effects, and three-dimensional thermal and electrical spreading resistance of the substrate. Simulations exhibit good agreement with experimental results for bulk Si and SiGe thin-film coolers. It turned out that in many spot cooling applications using two n - and p -elements electrically in series and thermally in parallel does not give significant improvement over single leg elements. This is in contrast to conventional thermoelectric modules and is due to the aspect ratio and special geometry of thin film coolers. With optimization of SiGe thin-film cooler, simulations predict it can provide over 16°C with cooling power density of over 2000 W/cm 2 .
    Microscale Thermophysical Engineering 12/2004; 9(1):99-118.

Publication Stats

186 Citations
19.42 Total Impact Points

Institutions

  • 2002–2011
    • University of California, Santa Cruz
      • • Jack Baskin School of Engineering
      • • Department of Electrical Engineering
      Santa Cruz, California, United States
  • 2005
    • University of California, Santa Barbara
      • Department of Electrical and Computer Engineering
      Santa Barbara, CA, United States
  • 2004
    • University of Missouri
      • Department of Mechanical and Aerospace Engineering
      Columbia, MO, United States