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ABSTRACT: This paper presents a low-phase-error wideband fractional-N frequency synthesizer. Differential tuning is described and a level shift circuit is proposed to obtain symmetrical tuning range. On-chip LDO regulator is designed to improve the power supply rejection for VCO. A voltage monitor is used to enhance the digital AFC technique to overcome the temperature variation. The synthesizer was implemented in a 0.18-mum CMOS process with a 16-mA supply current and a 1.47-mm<sup>2</sup> die area. The measured in-band phase noise is less than -97 dBc/Hz at a 10-kHz frequency offset and the integrated phase error is less than 0.75deg<sub>RMS</sub>. The measured reference spur is less than -71 dBc and the locking time is smaller than 20 mus.
Custom Integrated Circuits Conference, 2009. CICC '09. IEEE; 10/2009
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ABSTRACT: A fully integrated 1.175-2-GHz differentially tuned frequency synthesizer aimed for digital video broadcasting-terrestrial tuners is implemented in a 0.18-mum CMOS process. To maintain phase-noise optimization and loop stability over the entire output frequency range, techniques of constant loop bandwidth are proposed. The voltage-controlled oscillator gain K <sub>VCO</sub> and band step f <sub>res</sub> are both maintained by simultaneously adjusting the sizes of switched capacitors and varactors. Charge pump current I <sub>CP</sub> is programmed to compensate the variation of the division ratio N . The measured results show an in-band phase noise of -97.6 dBc/Hz at a 10-kHz offset and an integrated phase error of 0.63 <sup>deg</sup> from 100 Hz to 10 MHz. The measured variations of K <sub>VCO</sub> and f <sub>res</sub> are less than 12.5% and 4.5%, respectively. The variations of the measured phase noise at 10-kHz and 1-MHz frequency offsets are less than 1 dB. The measured 3-dB closed-loop bandwidth is 110 kHz and the variation is less than 9%. The chip draws 10-mA current from a 1.8-V supply while occupying a 2.2-mm<sup>2</sup> die area.
IEEE Transactions on Microwave Theory and Techniques 05/2009; · 1.85 Impact Factor
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IEEE International Solid-State Circuits Conference, ISSCC 2009, Digest of Technical Papers, San Francisco, CA, USA, 8-12 February, 2009; 01/2009
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ABSTRACT: A wideband CMOS variable gain low noise amplifier (VGLNA) used for TV tuner is presented. A single-to-differential (S2D) circuit other than an off-chip balun is applied for high gain mode and a resistive attenuator is for five steps (6 dB per step) attenuation in low gain mode. The performance of S2D, especially the noise factor is analyzed. The chip is implemented in a 0.18-mum 1P6M mixed-signal CMOS process. Measurements show that in the 50-860 MHz frequency range, the VGLNA achieves 15 dB maximum gain, 31 dB variable gain range, a minimum 3.8 dB noise figure and 2.6 dBm 11P3 at 15 dB gain while consumes 5.7 mA from a 1.8 V supply.
Solid-State Circuits Conference, 2008. A-SSCC '08. IEEE Asian; 12/2008
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ABSTRACT: A 12<sup>th</sup> order active-RC filter for DVB Tuner applications with automatic frequency tuning (AFT) is presented in this paper. The filter is implemented in Butterworth biquad structure. The AFT circuit is introduced to compensate the frequency variation by a 7-bits switched-capacitor array. The measurement results indicate that the precision of tuning circuit can be controlled less than plusmn2.3%, the in-band group delay variation is 70 ns, and the in-band IM3 achieves -60 dB with -27 dbm input power. This proposed filter circuit, fabricated in a SMIC 0.18 mum CMOS process, consumes 6 mA current with 1.8 V power supply.
Solid-State Circuits Conference, 2008. A-SSCC '08. IEEE Asian; 12/2008
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ABSTRACT: A fully differential charge pump is proposed in this paper. It adopts the replica technique to eliminate the effect of channel-length modulation, and the charging and discharging currents can match well in a wide output range. A rail-to-rail common-mode feedback circuit is employed to ensure the large swing of the charge pump unrestricted. The charge pump is designed and fabricated in SMIC 0.18 mum CMOS process. The measured reference spur-level is about -73 dBc and the in-band phase noise is nearly -90 dBc/Hz@lKHz. The power dissipation of the charge pump is only 1 mW.
Circuits and Systems, 2008. ISCAS 2008. IEEE International Symposium on; 06/2008
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ABSTRACT: A differential high linearity low-noise amplifier (LNA) based on a capacitor-cross-coupled topology is presented in this paper. An off-chip balun is used for providing DC-bias and canceling the channel thermal noise of the transconductance MOS transistors. The LNA uses NMOS load and provides an extra signal feed-forward and noise-canceling path. Analysis shows that the noise contribution of the transconductance MOST is only gamma/20 and the noise figure (NF) of the proposed LNA is 1 + 0.2gamma. The chip is implemented in a 0.18-mum MMRF CMOS process. Measured results show that in 50 M-860 MHz frequency range, the LNA achieved 15 dB gain, 2.5 dB NF, 8.3 dBm IIP3 and consumes only 4 mA current from a 1.8-V supply.
Solid-State Circuits Conference, 2007. ASSCC '07. IEEE Asian; 12/2007
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ABSTRACT: In this paper, a low noise high linearity mixer is presented, exploiting a switched transconductor topology. Its noise figure (NF) and linearity are analyzed particularly. The mixer chip is implemented in 0.18-mum RF CMOS process. The measurement result shows that the conversion gain of the mixer is about 8 dB, the SSB NF is about 11 dB, and the input-referred third-order intercept point (IIP3) is about 10.5 dBm. The chip consumes 10 mA at 1.8 V power supply and the size of the whole chip is 0.63 mm times 0.78 mm.
ASIC, 2007. ASICON '07. 7th International Conference on; 11/2007
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ABSTRACT: In this paper, a wide-band CMOS low-noise amplifier (LNA) is presented, in which the thermal noise of the input MOSFET is canceled exploiting a noise-canceling technique. The LNA is designed under input/output impedance matching condition. And its noise figure (NF) and linearity analysis are investigated particularly. The LNA chip is implemented in a 0.25-mum 1P5M RF CMOS process. Measurement results show that in 50-860 MHz, the gain is about 13.4 dB, the NF is from 2.4 dB to 3.5 dB, and the input-referred third-order intercept point (IIP3) is 3.3 dBm. The chip consumes 30 mW at 2.5-V power supply and the core size is only 0.15 mm times 0.18 mm.
Solid-State Circuits Conference, 2006. ASSCC 2006. IEEE Asian; 12/2006
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ABSTRACT: This paper proposes a novel 1-GHz LC oscillator differentially tuned by switched step capacitors, which is implemented in a 0.25mum 1P5M CMOS process. A period calculation technique (PCT) is adopted to analyze the differential tuning characteristic of switched step capacitors. Due to the symmetric oscillation waveforms, the differentially tuned LC VCO has 7 dB phase noise reduction in the 1/f <sup>3</sup> region compared to the single-ended tuned topology, and 23.6dB CMRR. It achieves phase noise -83 dBc/Hz, -107 dBc/Hz and -130 dBc/Hz respectively at 10-kHz, 100-kHz and 1-MHz offsets, while dissipating 3.3 mA current at 2.6 V power supply. Chip size is 0.82 mm times 0.84 mm
Asian Solid-State Circuits Conference, 2005; 12/2005
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ABSTRACT: An accurate 1.08-GHz CMOS LC voltage-controlled oscillator is implemented in a 0.35μm standard 2P4M CMOS process. In this paper we present a new convenient method of calculation of oscillating period. With this period calculation technique, the frequency tuning curves agree perfectly with the experiment. At a 3.3-V supply, the LC-VCO measures a phase noise of 82.2 dBc/Hz at a 10 kHz frequency offset while dissipating 3.1mA current. Chip size is 0.86mm × 0.82mm.
Design Automation Conference, 2005. Proceedings of the ASP-DAC 2005. Asia and South Pacific; 02/2005
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ABSTRACT: This paper describes a new prediction method of tuning curves of a LC-tank voltage-controlled oscillator (VCO) with period calculation technique. With this period calculation technique, the prediction of oscillator tuning curves is more accurate compared with the traditional harmonic approximation. The theoretical analyses are experimentally validated with a CMOS complementary LC-tank VCO implemented in 0.35μm 1P4M pure logic CMOS process.
Design Automation Conference, 2005. Proceedings of the ASP-DAC 2005. Asia and South Pacific; 02/2005
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Conference Proceeding:
Standard
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, ASP-DAC 2005, Shanghai, China, January 18-21, 2005; 01/2005
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ABSTRACT: In this paper, a distributed capacitance model (DCM) for monolithic inductors is developed to predict the equivalent parasitical capacitances of inductor. The ratio of the self-resonant frequency (f<sub>SR</sub>) of the differentially driven symmetric inductor (f<sub>SR_diff</sub>) to the f<sub>SR</sub> of the single-ended driven inductor (f<sub>SR_se</sub>) has firstly predicted and explained. Compared with an equivalent single-ended configuration, experimental data demonstrate that the differential inductor offers a 127% greater maximum quality factor (Q<sub>max</sub>) and a broader range of operating frequencies. Design guidelines have been obtained from DCM.
Solid-State and Integrated Circuits Technology, 2004. Proceedings. 7th International Conference on; 11/2004
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ABSTRACT: This paper presents a simple structure equivalent circuit model for multi-level spiral inductor on silicon substrates. Skin effect and proximity effect are well modeled by additional RL branch and mutual inductance. For multi-level inductors, since all metal wires couple laterally to each other through the substrate, coupling between wires and between metal layers can be modeled by a parallel combination of resistance and capacitance. Verification with measurement data from a series of multi-level spiral inductors in 2P4M Si process demonstrates accurate performance over wide band frequency range.
Microwave and Millimeter Wave Technology, 2004. ICMMT 4th International Conference on, Proceedings; 09/2004
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ABSTRACT: A new high-speed, programmable FIR filter is presented, which is a multiplierless filter with CSD encoding coefficients. We propose a new programmable CSD encoding structure to make CSD coefficients programmable. Compared with the conventional FIR structure with Booth multipliers, this coding structure improves the speed of filter and decreases the area. We design a 10-bits, 18-taps video luminance filter with the presented filter structure. The completed filter core occupies 6.8 × 6.8 mm of silicon area in 0.6 μm 2P2M CMOS technology, and its maximum work frequency is 100 MHz.
IEEE Transactions on Consumer Electronics 12/2002; · 0.94 Impact Factor
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ABSTRACT: In this paper, a high-performance all-digital quadrature frequency synthesizer/mixer applied to QAM modulation and demodulation is presented, which synthesizes 12-bit sine and cosine waveforms with a spectral purity of -83.0 dB. The synthesizer covers a bandwidth from DC to 100 MHz in steps of 0.0466 Hz with a corresponding switching speed of 5 ns at 200 MHz clock frequency. Also, it is capable of frequency, phase and quadrature amplitude modulation. In this design, an efficient ROM look-up table method for calculating the sine and cosine function is employed, and a compression algorithm that only calculates one-eighth sine function is adopted to reduce the volume of ROM. By taking advantage of sine and cosine symmetries, the size of the ROM look-up table is only 1/51 of that of traditional one. The resulting chip fabricated in 0 35 μm five-level metal CMOS process has a complexity of about 20,000 gates with core area of 200 × 100 mm<sup>2</sup>.
Circuits and Systems, 2002. MWSCAS-2002. The 2002 45th Midwest Symposium on; 09/2002
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ABSTRACT: A fully integrated 1.175 to 2 GHz differentially tuned frequency synthesizer aimed for DVB-T tuners is implemented in 0.18-mum CMOS. Techniques are proposed to make the loop bandwidth constant across the whole output frequency range to maintain phase noise optimization and loop stability. It exhibits in-band phase noise of -97.6 dBc/Hz at 10 kHz offset and integrated phase error of 0.63deg from 100 Hz to 10 MHz. The chip draws 10 mA from a 1.8 V supply while occupying 2.6 mm<sup>2</sup> die area.
Radio Frequency Integrated Circuits Symposium, 2008. RFIC 2008. IEEE;
