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ABSTRACT: In this paper an integrated SAW-less narrowband RF front-end for direct conversion wireless receivers is presented. The analysis of the feedback system shows a shift of the center frequency f<sub>RX</sub> for the overall RF bandpass filter from its nominal value f<sub>LO</sub>. The proposed architecture incorporates a notch filter at 2f<sub>LO</sub> to insure that there is no shift in f<sub>RX</sub>. The design has been implemented in 65nm CMOS process. It consumes 44mA from a single 1.2V supply. Simulation results show a rejection of more than 15dB in a bandwidth of +/-500MHz around 2GHz due to the additional feedback loop. The theoretical and simulation results are in close agreement.
Circuits and Systems (MWSCAS), 2010 53rd IEEE International Midwest Symposium on; 09/2010
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ABSTRACT: This brief proposes a scalable multichannel clock and data recovery architecture that exploits the synchrony of multiple point-to-point serial links and uses a single voltage-controlled oscillator (VCO) to drive multiple phase detection loops. The proposed architecture can be naturally reduced by design to an ensemble of weakly interacting delay-locked loops. As a result, the jitter peaking problem is asymptotically eliminated, which makes this architecture well suited for use in long-haul repeater chains. Moreover, it allows controlling VCO jitter transfer to the recovered clock without affecting data jitter transfer. The architecture is demonstrated both by a Verilog-A behavioral model along with a rigorous system and statistical analysis.
Circuits and Systems II: Express Briefs, IEEE Transactions on 06/2010; · 1.41 Impact Factor
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ABSTRACT: A single chip quad-band multi-mode (GSM900/ DCS1800/PCS1900/CDMA2K) direct-conversion RF receiver with integrated baseband ADCs is presented. The fully integrated RF receiver is implemented in a 90-nm single poly, six level metal, standard digital CMOS process with no additional analog and RF components. The highly digital multi-mode receiver uses minimum analog filtering and AGC stages, digitizing useful signal, dynamic DC offsets and blockers at the mixer output. The direct-conversion GSM front-end utilizes resistive loaded LNAs with only two coupled inductors per LNA. The GSM front-end achieves a 31.5 dB gain and a 2.1 dB integrated noise figure with a 5 dB noise figure under blocking conditions. The CDMA2K front-end utilizes a self-biased common-gate input amplifier followed by passive mixers, achieving wideband input matching from 900 MHz up to 2.1 GHz with an IIP3 of +8 dBm. The GSM receiver consumes 38 mA from a power supply of 1.5 V and CDMA2K receiver consumes 16 mA in the low band and 21 mA in the high band. The multi-mode receiver, including LO buffers and frequency dividers, ADCs, and reference buffers, occupies 2.5 mm<sup>2</sup>.
IEEE Journal of Solid-State Circuits 06/2006; · 3.23 Impact Factor
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ABSTRACT: In this paper, an approach to map the Bluetooth and 802.11b standards specifications into an architecture and specifications for the building blocks of a dual-mode direct conversion receiver is proposed. The design procedure focuses on optimizing the performance in each operating mode while attaining an efficient dual-standard solution. The impact of the expected receiver nonidealities and the characteristics of each building block are evaluated through bit-error-rate simulations. The proposed receiver design is verified through a fully integrated implementation from low-noise amplifier to analog-to-digital converter using IBM 0.25-μm BiCMOS technology. Experimental results from the integrated prototype meet the specifications from both standards and are in good agreement with the target sensitivity.
Circuits and Systems I: Regular Papers, IEEE Transactions on 06/2006; · 1.97 Impact Factor
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International Symposium on Circuits and Systems (ISCAS 2006), 21-24 May 2006, Island of Kos, Greece; 01/2006
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ABSTRACT: The implementation of a 3<sup>rd</sup>-order 50MS/s CT ΔΣ modulator with 5 levels of quantization, for a CDMA2k receiver, is presented. Its 9nVrms/√Hz input referred noise produces 80dB of DR in a 600kHz BW for signals as low as 70mVrms. It draws 4mA from a single 1.5V supply, uses a 90nm CMOS process and occupies 0.25mm<sup>2</sup>.
Solid-State Circuits Conference, 2005. Digest of Technical Papers. ISSCC. 2005 IEEE International; 03/2005
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ABSTRACT: The design of a dual-mode low-pass channel selection filter for a dual-standard 802.11b/Bluetooth direct conversion receiver is presented. The filter is an OTA-C, 5<sup>th</sup> order, Butterworth low pass structure. The OTA is implemented as a source-degenerated bipolar differential pair. Dual-mode operation, 600 kHz cut-off frequency for Bluetooth mode and 6 MHz for Wi-Fi mode, is achieved by switching the source-degeneration resistors and the capacitors. The filter operates from a single 2.5 V supply while consuming 2.7 mA and 0.9 mA for 802.11b and Bluetooth, respectively. It achieves 10 dBm in-band IIP3, 40 dBm out-of-band IIIP3 for both modes. The measured input referred noise density is -148.92 dBV/Hz and -140.48 dBV/Hz for 802.11b and Bluetooth, respectively.
Solid-State Circuits Conference, 2004. ESSCIRC 2004. Proceeding of the 30th European; 10/2004
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ABSTRACT: A fully integrated direct conversion receiver, supporting both Bluetooth and 802.11b standards, is implemented using IBM 0.25 μm BiCMOS technology. The RF front-end is shared between both standards while the baseband blocks are programmable for each receiving mode. All the components of the receiver from the LNA to the ADC are integrated using 19 mm<sup>2</sup> of silicon area. The current consumption of the chip is 41.3 mA/45.6 mA in Bluetooth/802.11b standard and the measured sensitivity is -91 dBm/-86 dBm, respectively.
Radio Frequency Integrated Circuits (RFIC) Symposium, 2004. Digest of Papers. 2004 IEEE; 07/2004
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ABSTRACT: A dual-mode direct-conversion 802.11b/Bluetooth receiver is integrated from LNA to ADC in a 0.25μm BiCMOS process. The baseband circuits are programmable to accommodate both standards while the RF front-end is shared. Die area is 21 mm<sup>2</sup>, and the IC consumes 45.6/41.3mA (802.11b/Bluetooth). Sensitivity is -86/-91dBm and IIP3 is -13/-13dBm.
Solid-State Circuits Conference, 2004. Digest of Technical Papers. ISSCC. 2004 IEEE International; 03/2004
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ABSTRACT: A general description of nonlinearities in pseudo differential operational transconductance amplifiers (OTA) with common-mode feedback (CMFB) is introduced. The effects of CMFB nonlinearities on the differential signals are evaluated and design tradeoffs including nonidealities are determined. A practical pseudo differential fully balanced fully symmetric OTA architecture with common-mode feedforward (CMFF) is used as a case study to probe the theory. The OTA has an inherent common-mode detector; hence, the CMFB circuit is efficiently implemented. The OTA is used to implement a 100-MHz fourth-order linear-phase OTA-C filter.
IEEE Transactions on Circuits and Systems II Analog and Digital Signal Processing 11/2003;
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ABSTRACT: A low-voltage fourth-order RF bandpass filter structure based on emulation of two magnetically coupled resonators is presented. A unique feature of the proposed architecture is using electric coupling to emulate the effect of the coupled inductors, thus providing bandwidth tuning with small passband ripple. Each resonator is built using on-chip spiral inductors and accumulation-mode pMOS capacitors to provide center frequency tuning. The filter has been implemented in HP 0.5-μm CMOS process and occupies an area of 0.15 mm<sup>2</sup>. It consumes 16 mA from a single 2.7-V supply at a center frequency of 1.84 GHz and a bandwidth of 80 MHz while providing a passband gain of 9 dB and more than 30 dB of image attenuation for an IF frequency of 100 MHz. The measured output 1-dB compression point and output noise power spectral densities are -16 dBm and -137 dBm/Hz, respectively. This results in a 1-dB compression dynamic range of 42 dB. The filter minimum power supply voltage for proper operation is 2 V. The chip experimental results are in good agreement with theoretical results.
IEEE Journal of Solid-State Circuits 08/2003; · 3.23 Impact Factor
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ABSTRACT: A pseudo-differential fully balanced fully symmetric CMOS operational transconductance amplifier (OTA) architecture with inherent common-mode detection is proposed. Through judicious arrangement, the common-mode feedback circuit can be economically implemented. The OTA achieves a third harmonic distortion of -43 dB for 900 mV<sub>pp</sub> at 30 MHz. The OTA, fabricated in 0.5-μm CMOS process, is used to design a 100-MHz fourth-order linear phase filter. The measured filter's group delay ripple is 3% for frequencies up to 100 MHz, and the measured dynamic range is 45 dB for a total harmonic distortion of -46 dB. The filter consumes 42.9 mW per complex pole pair while operating from a ±1.65-V power supply.
IEEE Journal of Solid-State Circuits 05/2003; · 3.23 Impact Factor
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ABSTRACT: A low-power quadrature direct digital frequency synthesizer (DDFS) is presented. Piecewise linear approximation is used to avoid using a ROM look-up table to store the sine values as in a conventional DDFS. Significant saving in power consumption, due to the elimination of the ROM, renders the design more suitable for portable wireless communication applications. To demonstrate the proposed technique, a quadrature DDFS has been implemented using 0.5-μm CMOS process and occupies an active area of 1.4 mm<sup>2</sup>. It consumes 8 mW at 100 MHz and operates from a single 2.7-V supply. The spurious-free dynamic range is better than 59 dBc at low synthesized frequencies and the frequency resolution is 1.5 kHz.
IEEE Journal of Solid-State Circuits 11/2002; · 3.23 Impact Factor
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ABSTRACT: A low-power quadrature direct digital frequency synthesizer (DDFS) is presented. Piecewise linear approximation is used to avoid using ROM lookup table to store the sine values. ROM elimination has resulted in significant power and area savings. The proposed DDFS has been implemented using 0.5µm CMOS process and occupies 1.4mm<sup>2</sup>area. It achieves an extremely low power consumption of only 8mW at 100MHz and operates from a single 2.7V supply. The SFDR is better than 58dBc at low synthesized frequencies and the frequency resolution is 1.5kHz.
Solid-State Circuits Conference, 2002. ESSCIRC 2002. Proceedings of the 28th European; 10/2002
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ABSTRACT: A pseudo differential fully balanced CMOS OTA architecture with inherent common mode detection is proposed. Through judicious arrangement, the common-mode feedback circuit can be economically implemented. The OTA achieves a good CMRR and is suitable for low voltage operation. As an example of the applications of the proposed OTA, a 100MHz 4th order linear phase OTA-C filter is presented. The measured group delay ripple is 3%, the filter dynamic range is 45dB. It consumes 42.9mW per complex poles.
Solid-State Circuits Conference, 2002. ESSCIRC 2002. Proceedings of the 28th European; 10/2002
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ABSTRACT: A low-voltage 4th order RF bandpass filter structure based on a two magnetically-coupled resonators prototype is presented. Each resonator is built using on-chip spiral inductors and accumulation-mode PMOS capacitors to provide center frequency tuning. The proposed architecture is using electric coupling to emulate the effect of the transformer thus providing bandwidth tuning with small passband ripple. The filter has been implemented in HP0.5 µm CMOS process and occupies an area of 0.15mm<sup>2</sup>. It consumes 16mA from a single 2.7V supply at a center frequency of 1.84GHz and a bandwidth of 80MHz while providing a passband gain of 9dB. The measured output 1 dB compression point, and output noise power spectral density are -40dBm and -161dBm/√Hz, respectively. This results in a 1dB compression dynamic range of 42dB.
Solid-State Circuits Conference, 2002. ESSCIRC 2002. Proceedings of the 28th European; 10/2002
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ABSTRACT: This paper presents a comparative study of three single-stage high frequency linearized OTAs for the design of high-performance continuous-time filters. The advantages and disadvantages of each structure are discussed. The two pseudo-differential OTAs are suitable for very low-voltage applications. One OTA is suitable for very high frequency applications and the other one has a very large linear signal swing and a large transconductance tuning range. The third OTA is based on complementary differential pairs and has very low power consumption. Design examples and experimental results are presented to demonstrate the performance characteristics of each structure.
Circuits and Systems, 2002. MWSCAS-2002. The 2002 45th Midwest Symposium on; 09/2002
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ABSTRACT: This paper presents different design considerations of active Q-enhanced LC bandpass filters. An architecture for implementing high order filters is proposed. It uses electric coupling to emulate the effect of the transformer, thus providing bandwidth tuning with small passband ripple.
Circuits and Systems, 2002. MWSCAS-2002. The 2002 45th Midwest Symposium on; 09/2002
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ABSTRACT: This paper presents the implementation of an incremental A/D converter for a power supply voltage of ±1 V. The design relies on using floating gate technique in order to reduce the effect of nonlinear settling due to possible saturation of the input stage and to achieve good performance under low voltage operation. The converter has been implemented in 0.5 μm CMOS technology with V<sub>TN</sub>=0.65 V and V<sub>TP</sub>=-0.90 V. The chip prototype occupies an area of 0.2 mm<sup>2</sup>. The converter has been designed for 15 bits of accuracy. Due to the limited accuracy of the measurement equipment, we were able to measure 11 bits of resolution. The converter operates at a clock frequency of 500 kHz and consumes less than 1 mW.
Circuits and Systems, 2002. ISCAS 2002. IEEE International Symposium on; 02/2002
