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ABSTRACT: A selective internal reset mechanism that allows the burst-mode TIA to recover a burst-mode signal as a stand-alone device in EPON is discussed. Using step AGC, the TIA achieves a DR of 27dB and a sensitivity of -31dBm with a PIN photodiode. Moreover, with internal reset, the loud/soft ratio is also 27dB within 100ns guard and preamble times.
Solid-State Circuits Conference, 2007. ISSCC 2007. Digest of Technical Papers. IEEE International; 03/2007
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ABSTRACT: An all-CMOS variable gain amplifier (VGA) that adopts a new approximated exponential equation is presented. The proposed VGA is characterized by a wide range of gain variation, temperature-independence gain characteristic, low-power consumption, small chip size, and controllable dynamic gain range. The two-stage VGA is fabricated in 0.18-mum CMOS technology and shows the maximum gain variation of more than 95 dB and a 90-dB linear range with linearity error of less than plusmn 1 dB. The range of gain variation can be controlled from 68 to 95 dB. The P1dB varies from - 48 to - 17 dBm, and the 3-dB bandwidth is from 32 MHz (at maximum gain of 43 dB) to 1.05 GHz (at minimum gain of - 52 dB). The VGA dissipates less than 3.6 mA from 1.8-V supply while occupying 0.4 mm<sup>2</sup> of chip area excluding bondpads
Circuits and Systems I: Regular Papers, IEEE Transactions on 09/2006; · 1.97 Impact Factor
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ABSTRACT: This brief presents a CMOS burst-mode optical transmitter suitable for use in 1.25-Gb/s Ethernet passive optical network applications. Based on feedback from the monitoring photodiode, in order to control consecutive burst data the proposed transmitter in this brief uses a reset mechanism, which allows fast responses from the beginning of a high-speed input burst. The chip is fabricated in mixed-mode 0.18-μm CMOS technology and measurements are implemented in a chip-on-board configuration using a pig-tailed type Fabry-Perot laser. Under burst-mode operation of 1.25-Gb/s pseudorandom binary sequences, measurements show about 1-dBm averaged transmitted optical power with an over 12-dB extinction ratio over a wide temperature range.
Circuits and Systems II: Express Briefs, IEEE Transactions on 12/2005; · 1.41 Impact Factor
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ABSTRACT: This paper presents a new high performance wideband CMOS transimpedance amplifier (TIA) for 2.5 Gbps optical transceiver. Our proposed TIA self-regulating adjusts the controllable inductive peeking load and feedback resistances whenever overload condition occurs. The proposed TIA design exhibits bandwidth enhancement, lower input referred noise, and higher amplifier stability. This TIA has 69 dBOmega gain at 3 dB bandwidth, 7.2 pA/radicHz input referred noise and good performance of eye diagram. The TIA operates at the 3.3 V supply voltage, and dissipates about 34 mA for whole circuit. The simulation is accomplished with 1 pF capacitance and 0.85 A/W responsibility photodiode model
Circuits and Systems, 2005. 48th Midwest Symposium on; 09/2005
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ABSTRACT: This paper presents a burst-mode receiver for 1.25-Gb/s Ethernet PON system using mixed-mode CMOS 0.18-μm technology. With the modified cell-based AGC function and differential feed-forward topology, the receiver achieves sensitivity of -26.4 dBm, overload of -5.4 dBm, and a loud/soft ratio of 21 dB while keeping the low-voltage positive emitter-coupled logic (LVPECL) differential output level fully compliant with the ethernet passive optical network (EPON) standard. Unlike other burst-mode receivers, the design obtains fast response even without a reset signal from the network layer by creating a reset signal internally based on the incoming signal. This setting allows for simple system design. The overall architecture and several blocks are optimized in accordance with internal reset creation. Minimum guard time and preamble time are 250 and 50 ns, respectively; all timing parameters are better than the current EPON standard. The prototype contains all components on-chip that occupies 0.9×1.9 mm<sup>2</sup> and consumes 160 mA current from a 3.3-V supply.
IEEE Journal of Solid-State Circuits 01/2005; · 3.23 Impact Factor
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ABSTRACT: This paper presents a burst-mode 1.25 Gb/s transmitter, suitable for use in Ethernet PON (E-PON) applications. With a burst enable signal, the transmitter proposed in this paper allows fast responses from the beginning of high-speed burst data while a conventional automatic power control circuit, based on feedback from a monitor photodiode, was used. The chip was implemented in 0.18 μm CMOS technology and occupies an area of 0.9×0.75 mm<sup>2</sup> with about 260 mW power dissipation under 3.3 V supply. Measurements show a stable transmitted optical power over a wide temperature range (-40°C to 80°C) with above 10 dB extinction ratio.
Solid-State Circuits Conference, 2004. ESSCIRC 2004. Proceeding of the 30th European; 10/2004
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ABSTRACT: A fully integrated fiber-optic transmitter chip for gigabit Ethernet applications has been implemented in a CMOS technology. For controlling the transmitted optical power so to obtain reliable and constant averaged optical power, the transmitter proposed in this paper uses separated bias and modulation currents control circuits based on the feedback from the monitoring photo-diode (MPD). The chip was fabricated in a mixed-signal analog CMOS technology with 0.18mum gate length and measurements were implemented in a chip-on-board configuration (COB) using pig-tailed FP laser. Under the burst-mode operation of 1.25Gb/s PRBS, measurements show about 0.5dBm transmitted optical power with above 11dB extinction ratio over a wide temperature range. Based on the measurements, this work complies with the EPON IEEE P802.ah standard
Advanced Communication Technology, 2005, ICACT 2005. The 7th International Conference on; 02/2001
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ABSTRACT: This paper proposes a new preamplifier topology on 0.35µm CMOS process for OLT receiver in 155Mb/s ATM-PON system. The preamplifier consists of transimpedance and limiting amplifiers. It has a unique combination of features including differential outputs with negligible offset; low input referred noise current density of 1.6pa/√Hz; high loud/soft ratio of more than 26dB; high maximum input power level of – 8.5dBm with extinction ratio of 10dB. The preamplifier responses within 1 bit after reset as the worst case. On the whole, the preamplifier fully complies with ITU-T Recommendation G.983.1, as indicated in simulation result. The performance is achieved by applying a new auto-gain-control transimpedance amplifier topology and a new limiting amplifier with auto-offset-cancellation function. Two external transistors are required to form Positive Emitter Coupled Logic (PECL) compliant output interface matched to 50Ω. The ntroduction of this IC can help make system design more flexible and economical. Using a combination of auto-gain-control transimpedance amplifier and auto-offset-cancellation limiting amplifier, the design achieves high sensitivity (less than -34.6 dBm) and wide dynamic range (more than 26dB). The fact that input power level varies largely between consecutive bursts means a reset mechanism is needed to put circuit back to initial condition after each burst. Fast response circuit is required so that system can get back to normal operation in just a few bits after being reset. According to Rec. G.983.1 [9], there will be at least 4 bit periods called guard time after each burst to avoid collision, in which no signal is transmitted from any transmitter in the system. Reset pulse is assumed to appear during the last 3 bit periods of guard time. It's the best arrangement because at that time receiver is under the same condition for every burst. This design has recovery time of 1 bit after reset in the worst case when a lowest-level burst follows a highest-level burst. 2. Circuit design 2.1. Topology selection Keywords: burst mode, preamplifier, ATM-PON Block diagram of the preamplifier is given in Fig.2. The amplifier consists of a transimpedance (TZ) stage, a single-to-differential (S2D) stage and four consecutive limiting amplifiers. Feed-forward topology is chosen due to its simpler, less stringent requirements compare to feedback one [6]. But different from other designs [2], [6], in this work the level-hold circuits is used in S2D stage only. After that, signal is amplified by a suitable combination of auto-offset-cancellation limiting amplifiers (LA-AOC1 and LA-AOC2) and simple limiting amplifiers (LA-gain and LA-Buffer). After S2D stage, the LA-AOC1 stage is needed to suppress offset created by the S2D stage during conversion. Therefore it has only 7 dB of gain but 15 dB offset compression. The LA-AOC2 has much higher offset suppression because at that stage, voltage swing is high.The arrangement gives completely symmetric outputs at negligible offset level.
