Room-temperature quantum confinement effects in transport properties of ultrathin Si nanowire field-effect transistors.

Abstract

Quantum confinement of carriers has a substantial impact on nanoscale device operations. We present electrical transport analysis for lithographically fabricated sub-5 nm thick Si nanowire field-effect transistors and show that confinement-induced quantum oscillations prevail at 300 K. Our results discern the basis of recent observations of performance enhancement in ultrathin Si nanowire field-effect transistors and provide direct experimental evidence for theoretical predictions of enhanced carrier mobility in strongly confined nanowire devices.

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Room-Temperature Quantum Confinement Effects in Transport
Properties of Ultrathin Si Nanowire Field-Effect Transistors
Kyung Soo Yi,*,†,§Krutarth Trivedi,‡Herman C. Floresca,†Hyungsang Yuk,†Walter Hu,‡
and Moon J. Kim*,†,#
†Department of Material Science and Engineering and‡Department of Electrical Engineering, University of Texas at Dallas,
Richardson, Texas 75080, United States
§Department of Physics, Pusan National University, Busan 609-735, Korea
#Department of Nanobio Materials and Electronics, World Class University, Gwangju Institute of Science and Technology, Gwangju
500-712, Korea
*
S Supporting Information
ABSTRACT: Quantum confinement of carriers has a substantial impact on nanoscale device operations. We present electrical
transport analysis for lithographically fabricated sub-5 nm thick Si nanowire field-effect transistors and show that confinement-
induced quantum oscillations prevail at 300 K. Our results discern the basis of recent observations of performance enhancement
in ultrathin Si nanowire field-effect transistors and provide direct experimental evidence for theoretical predictions of enhanced
carrier mobility in strongly confined nanowire devices.
KEYWORDS: Quantum confinement effects, Si nanowires, room-temperature quantum oscillations, top-down patterning,
ultrathin Si nanowire transistor
Q
ation.1,2However, experimental study of quantum confinement
effects was mostly limited to ultralow temperatures until recent
years due to relatively large channel diameters of devices.3,4For
practical applications of quantum characteristics, it is crucial for
such effects to manifest at room temperature, which naturally
dictates the size of the channel be reduced well into single-digit
nanometer range so that the quantum size effect is able to
overcome thermal broadening. In recent years, quantum
oscillatory behavior has been reported to persist at elevated
temperatures in one-dimensional (1D) devices with reduced
dimensions.5−7There has been considerable effort to improve
key device parameters such as transfer conductance and carrier
mobility of such narrow Si nanowire (SiNW) devices.8−10More
recently, it has been possible to lithographically (top-down)
fabricated SiNW FETs on silicon-on-insulator (SOI) substrates
with device diameters as small as 3 nm,11,12and significant
performance enhancement has been reported at 300 K in top-
down patterned sub-5 nm p-Si [110] NW FETs.11Here, we
uantum confinement of carriers has an extensive
influence on the physics of nanoscale device oper-
demonstrate quantum confinement effect in transport proper-
ties of ultrathin p-Si FETs at room temperature. Clear plateau-
like structures in drain−source current (IDS) are revealed in the
subthreshold region of sub-5 nm p-SiNW FETs at 300 K.
Oscillations in both transconductance (gM) and channel
conductance (gD) are analyzed with respect to quantum
confinement-induced subband structure. The genuine oscil-
latory behaviors of conductance and carrier mobility are
understood in terms of strong confinement of carriers in
quantized 1D subband structure with corresponding unique 1D
density of states (DOS). We compile the findings of our study
into a framework to present clear experimental evidence of
measurable quantum confinement effects (at 300 K) and also
justify the recently reported enhanced carrier mobility in sub-5
nm SiNW FETs at room temperature.11,13
Received:
Revised:
Published: November 23, 2011
September 16, 2011
November 7, 2011
Letter
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Method. To demonstrate quantum size effects at room
temperature, we fabricated sub-5 nm thick Si[110] NW FETs
lithographically on a SOI substrate, and performed high-
resolution transmission electron microscopy (HR-TEM)
imaging to confirm dimensions and uniformity of channel
bodies in measured devices. Figure 1 shows a three-dimensional
(3D) schematics of the device and HR-TEM images of the
cross section of a nanowire body before (a) and after (b)
thermal oxidation. All electrical transport measurements were
performed in air at room temperature using a shielded probe
station with triax connectors in order to minimize RF radiation
noise. (See more details of SiNW device fabrication and
transport measurements in ref 11.) After electrical character-
ization, cross section of each device was prepared with focused
ion beam and imaged by HR-TEM to measure dimensions and
examine morphology. Cross sections of the SiNWs showed a
single-crystalline surface having a nearly circular and smooth
profile with dimensions as low as ∼3 nm. (See ref 11 for
additional HR-TEM images and interfacial details.) In these Si-
NW FETs, two bias fields are provided from external sources:
the transverse gate voltage applied to the back-gate electrode
(VBG) determines the effective width of the channel and the
carrier density inside the channel, while the longitudinal drain−
source voltage (VDS) transports carriers through the channel
body.
Quantum Confinement in 1D SiNW FETs. First, we
identify quantum size effects in transfer characteristics of p-
SiNW FETs. As illustrated in Figure 1, the channel body of
ultrathin SiNW FETs is confined in both [001] (top) and
[11̅0] (sides) directions, so that motion normal to [110] is
restricted physically by the SiNW channel body and the carriers
(holes) are free to move only in the [110] direction, producing
a series of quantized energy levels; each energy level forms a
subband. Subband energies and hence intersubband structure
depend strongly on the boundary conditions of quantum
confinement, which is closely related to the cross sectional
shape of NWs. Each sub-5 nm SiNW essentially forms a 1D
system of electrons, since the diameter of the NWs is close to
the wavelength of an electron (∼10 nm). The corresponding
1D subband structure results in a series of sawtooth-like
oscillatory DOS.14,15(See Figure S1 in Supporting Informa-
tion.)
As shown in Figure 2, the source−drain current IDSincreases
quasi-linearly at low back-gate voltage |VBG|. However, when
|VBG| is increased further, the channel current starts to increase
superlinearly and several steplike and oscillatory structures are
observed in drain current and transconductance, respectively.
Clear shoulders or steplike structures are visible in IDSfor low
gate voltages, and this observation is repeated in IDS−VBG
curves for p-SiNW FETs of various body lengths, implying that
this is related to inherent properties of the strongly confined
1D structure of our NW FETs. This observation is in close
agreement with theoretical model analysis of 1D transport,16
which prescribes oscillatory quantum features in transfer
characteristics in NW FETs. Each steplike feature occurs at a
“threshold” voltage corresponding to the occupation of a new
1D subband by the carriers in the confined device. As |VBG| is
increased, the number of subband conduction channels
increases and gM(= ∂IDS/∂VBG|VDS=const.) continues to disclose
repeated oscillatory behavior. Drain current fluctuations in the
regime of subthreshold gate voltages are usually observed only
at ultralow temperature and small drain bias.3,4,17However,
such quantum oscillation can persist even at room temperature
if NW cross section gets sufficiently small,5−7,11so that
intersubband separation becomes large enough to counter
thermal broadening. As shown in Figure 2, along with steplike
structures in IDSof the SiNW FET, gMshows corresponding
periodic oscillation with valleys corresponding to the flat
regions of IDS, despite large thermal broadening expected at 300
K. The average period of oscillatory peaks for low VDSis
approximately Δ|VBG| ∼ 0.4 V. The subband separation
equivalent to the gate voltage spacing Δ|VBG| ∼ 0.4 V is ΔE
≃ 55 ± 5 meV, obtained by numerically solving coupled
equations [eqs 2 and 4 in ref 16] for 1D carrier density and
drain current in the NW channel at VDS= 50 mV. The on-
Figure 1. Schematics of SiNW device and HR-TEM image. Three-
dimensional schematic of a back-gated SiNW FET patterned on a
silicon-on-insulator (SOI) substrate of buried oxide (BOX) and a HR-
TEM image of an oxidized Si[110] NW channel body cross section
before (a) and after (b) thermal oxidation.
Figure 2. Drain current and transconductance characteristics of a
SiNW FET at 300 K. The nanowire has a cross section of 4.3 nm × 5.1
nm. The inset shows characteristics of a Si nanobelt (SiNB) FET with
a cross section of 4.3 nm × 161 nm for comparison. The data are of p-
MOS devices; the horizontal axis is shown as a magnitude of back-gate
voltage for convenience.
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current spectrum shown in Figure 2 indicates that near-
threshold carrier conduction (|VBG|∼ few volts) occurs through
several subband channels.
Transfer characteristics of NW FETs with very dissimilar
cross sectional profile would be different, since quantum
confinement effects are closely related to channel boundary
conditions.15(See Figures S2−S4 in Supporting Information
for more on transfer characteristics.) The dissimilarity between
the transconductance characteristics of Si-FETs patterned with
a NW (Figure 2) versus a NB (inset of Figure 2) is physically
plausible, recalling features in the DOS of the 1D versus 2D
structures. A Si FET consisting of a NW with a cross section of
4.3 nm × 3.6 nm is essentially a 1D system with a sawtooth like
DOS but that of a NB with cross section of 4.3 nm × 161 nm is
a quasi-2D system with stairlike DOS.14,15(See Supporting
Information Figure S1 for the DOS.) Carrier confinement and
the corresponding DOS can result in oscillations in carrier
conductance and mobility. The transfer characteristics of the
NB FET (inset of Figure 2) show fast increase of IDSwith gate
voltage, while gM shows uniformly increasing conductance
peaks with larger interpeak separation, which is an indication of
the ladderlike 2D DOS profile resulting from the accumulated
contributions of individual 2D subband channels. Instead, the
characteristics of the NW FET reveal relatively quick current
saturation accompanied with reduction of gMfor increasing gate
bias, implying behavior of inverse-square-root singular 1D DOS
at the bottom of each 1D subband. We also note that
geometrically narrower dimensions of “cylindrical” NWs result
in both nonuniformly spaced and larger subband separations,
but laterally confined NBs resemble a quasi-2D electron gas of
uniformly spaced subband structure (with increasing separa-
tions for higher subbands).15
Channel Conductance Behavior and Intersubband
Spectroscopy. Here, we identify quantum size effects in
channel conductance characteristics and related intersubband
separations in p-SiNW FETs. For a given value of VBG, the
channel conductance, gD(= ∂IDS/∂VDS|VBG=const.), also varies with
VDS. (See Figure S5 in Supporting Information.) The periods of
repeated structures in IDScan be obtained by analyzing gDin
terms of VDS, and 1D intersubband separation can be
determined from the gDcharacteristics with VDS.18Figure 3a
shows a contour representation of dgD/dVBG, at 300 K, as
functions of VDSand VBG. Patterns of strong oscillations in dgD/
dVBGare clearly visible. The dark (blue) areas refer to the
regions of quickly increasing channel conductance, while light
(green) areas represent the regions of quickly decreasing
channel conductance. The zeros and high values of dgD/dVBG
correspond to conductance plateaus and interplateau transition
regions in IDS−VDScurve. Figure 3b illustrates measured IDS−
VDScharacteristics of a p-SiNW FET for various values of VBG
at 300 K and corresponding gD−VDS(curves for VBG= −0.3
and −0.9 V shown). Strong oscillations in gDwith both biases
VDSand VBGare clearly seen with amplitude of oscillations
increasing at higher values of VDSand VBG. For IDS−VDScurves,
the VBGis changed in −0.2 V steps and the lowest trace in the
figure is for VBG= −0.3 V. In general, IDSincreases with VDSand
|VBG| because both the energy states for current flow and the
number of 1D conduction channels increase,16and gDshows
strong oscillation with increasing VDS. In Figure 3b, stairlike
increase in IDS(VDS) is seen, and we find that the peaks in gDare
nearly uniformly spaced. It is also apparent that the period of gD
increases slightly as the magnitude of back-gate voltage VBG
increases, implying that a higher gate field gives rise to further
confinement of the carriers in the channel body, leading to
increased separation between subbands; the transverse gate
field induces further confinement (“field-induced confine-
ment”) of the carriers in the narrow channel body.
From the gD−VDScurves at a given VBG, the subband
separation ΔEn+1,n can be extracted. (See Supporting
Information Text 5.) Let us consider the case of the equilibrium
chemical potential μ0(= EF) located somewhere between
subband energies Enand En+1. (See Supporting Information
Figure S1.) As VDSis increased slowly, IDSremains constant
staying on the same plateau, waiting until either μSgets equal to
En′+1(V′DS) or μDequal to En′ (V′DS) at V′DSso that a new
subband channel opens and IDSincreases to a new value I′DS.
On increasing VDS, extrema in gD(VDS) can occur at
characteristic values of V′DS. If we let the two nearest maxima
of gD(VDS) occur at the drain voltages V1 and V2, the
corresponding intersubband separation is given by ΔEn+1,n=
eΔVDSwith ΔVDS= V2− V1.19Therefore, the period of peaks,
ΔVDS, corresponds to the subband separation of the channel
Figure 3. Channel transport behavior of SiNW FET at 300 K. (a) Contour representations of channel conductance derivative (dgD/dVBG) as
functions of VDSand VBGof a SiNW FET with cross section of 4.3 nm × 5.7 nm. (b) Drain current and channel conductance characteristics. The
channel conductance traces (bottom two curves) are offset in the vertical direction for clarity and conductance minima are indicated for VBG= −0.3
and −0.9 V, respectively.
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body. From the gD(VDS) behavior in Figure 3b, we obtain
ΔEn+1,n∼ 65 ± 10 meV for the low-lying few subbands in the p-
SiNW FET with cross section of 4.3 nm × 5.7 nm.
Remembering that the subband separation increases with the
gate bias in a given channel body and is inversely proportional
to the square of the channel radius,15our experimental value of
65 ± 10 meV is in accord with a theoretical prediction of ∼50
meV for p-SiNW FET of 5 nm × 5 nm cross section.20For an
order-of-estimation of subband separations in SiNWs, let us
take a p-SiNW body as an infinitely confined cylindrical 1D
electron system of radius r0treating gate oxide as an infinite
potential barrier to Si channel body even though the valence-
band offset of SiO2−Si is ∼4.5 eV.21The lowest two subband
separations ΔEn+1,nare 58.1 and 53.1 meV if we use 2r0= 5 nm
for NW diameter (71.8 and 65.6 meV if we use 2r0= 4.5 nm)
and m* = 0.15 m0of light-hole effective mass in the [110]
direction, where m0is the free-electron mass. (See Supporting
Information Text 3.) The lowest hole subband is of light
holelike character.20This order-of-magnitude estimation of
intersubband separation is also in agreement with our
experimentally extracted value (ΔEn+1,n∼ 65 ± 10 meV) for
low-lying subbands in our p-SiNW FET. This extracted
subband separation at 300 K corresponds to ΔEn+1,n≃ (1.7
± 0.24) kBT or in terms of thermal energy to Θ ≃ 510 ± 72 K,
which is about one-half of the theoretical thermal broadening
criterion (ΔE ≃ 3.5 kBT) for clear resolution of quantum
oscillations in mesoscopic transport measurements.2,22Hence,
the presence of measurable quantum oscillatory behavior in our
p-SiNW FETs at room temperature is well justified.
Confinement-induced quantum oscillatory behavior is known
to be observable provided that the source−drain bias eVDSis
not much larger than subband separation ΔEn,n′. For small VDS,
nearly flat and parallel subband channels are expected to
produce clear oscillations in source−drain transfer character-
istics as far as eVDSis not much larger than a few times the
intersubband separation ΔEn,n′.17Under a strong source−drain
bias field, the confinement potential is greatly tilted down along
the channel by the drain bias such that the gate field can induce
more carriers easily. When the chemical potential at the drain
side μDis pulled down drastically, the effective channel body
length is significantly reduced and, as a result, the quantum
mechanical interference effect can be visible in transport
parameters such as conductance and mobility of short-length
SiNW FETs in the quasi-ballistic regime.23,24Park et al. also
report enhanced drain current oscillations in inversion mode of
their Si FET for high VDSalbeit at low temperature.25(See
Figure 3 in ref 25.) Nevertheless, the continuing (sometimes
much enhanced) oscillatory behavior in IDS−VBGand gD−VBG
at higher VDSin our p-SiNW FETs is not fully understood yet.
(See Supporting Information Figure S5.) One possible source
of this observed effect could be related to strong electric field-
induced intersubband scattering near the drain.26We suppose
that extremely nonequilibrium high field dielectric response
would be responsible for the persisting oscillatory behavior at
high drain−source electric field,27and more rigorous analysis
such as nonequilibrium Green function approach to quantum
transport equations28would provide microscopic understand-
ing of carrier transport characteristics of such ultrathin quantum
devices.
Field-Effect Mobility Behavior of SiNW FETs. Here, we
identify quantum size effects in carrier mobility of p-SiNW
FETs. Field-effect mobility (μ) of conventional MOSFETs is
written as μ = (gML)/(VDSCoxW), where L, W, and Cox(≡ C/
(LW)) are the gate length, width, and the gate oxide
capacitance per unit area, respectively. Therefore, mobility
characteristics should also show oscillatory behavior with
respect to gate voltage, similar to gMof the SiNW FETs. For
reliable determination of C, finite element mesh simulation was
performed using COMSOL package with the specific geometry
of each device, as measured by HR-TEM imaging.11Our
simulated capacitance gives Cox ≃ 4.0 mF/m2. Mobility
characteristics of p-SiNW FETs are shown in Figure 4 in
terms of |VBG| with VDS= 50 mV at 300 K. Figure 4a shows μ of
p-SiNW FETs for channel lengths of 2, 3, and 10 μm. In
obtaining the mobility curves shown in Figure 4, we used C =
4.15 × 10−17F, 6.22 × 10−17F, and 2.05 × 10−16F for channel
length 2, 3, and 10 μm, respectively.
The mobility shows clear oscillatory behavior with VBG,
similar to gM. The periodic character of the 1D DOS is directly
reflected as the periodic oscillation in carrier mobility of the
SiNW FETs through the simple relation μ ∝ τ ∝ 1/DOS,
where 1/τ is some effective scattering rate. Decrease (increase)
in μ with |VBG| corresponds to increase (decrease) in the DOS.
As the gate bias increases, gradual occupancy of additional
subbands by carriers results in increase of drain current and the
steepest current increase (and, hence, a mobility peak) occurs
when a new subband channel opens up for carrier transport;
the oscillatory behavior occurs when carriers must “wait” for the
Figure 4. Field-effect mobility characteristics of Si FETs of various channel lengths and widths at 300 K. (a) Channel length dependence for three
different NW devices with nanowire height of 4.3 nm and width of ∼5.7, 5.1, and 3.6 nm for channel length of 2, 3, and 10 μm, respectively. (b)
Comparison of mobilities in NW and NB devices of 3 μm length. The widths of NW and NB devices are 5.1 and 161 nm, respectively.
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Fermi level in the channel to rise to include the subsequent
subband.29Figure 4a shows that peak mobility occurs at
relatively low gate biases near |VBG| ∼ 2 V, and the overall
mobility is enhanced in the NW devices with longer channel
body. Although the NW device with 10 μm long channel body
shows reduced transconductance behavior (as illustrated in
Figure S2 in Supporting Information), it produces the highest
peak mobility value, approaching over ∼900 cm2V−1s−1. This
apparent feature is attributed to the fact that relative carrier
mobility of various SiNW FETs is controlled by the product of
gM(L/W), since the remaining factor, VDSCox, in the expression
μ = (gML)/(VDSCoxW) is independent of channel cross
sectional dimensions; for example, L/W is largest for the 10
μm long nanowire device due to long length and smallest NW
cross section. The fact that gMdoes not scale proportionally
with (L/W)−1implies an intrinsic increase of mobility in
nanowires with a smaller cross section, like the 4.3 nm × 3.6
nm NW device in Figure 4a (also see Figure S2 in Supporting
Information). Figure 4b shows field-effect mobility character-
istics of 3 μm long SiNW FET with cross section of 4.3 nm ×
5.1 nm and SiNB FET with cross section of 4.3 nm × 161 nm.
The disparity in gate bias dependence of field-effect mobility in
NW FETs as compared to NB FETs resembles the
corresponding disparity in transport and transconductance
characteristics of the two devices seen in Figure 2. (See also
Figure S4 in Supporting Information.) The overall performance
of SiNW and SiNB devices is distinctive due to the unique
DOS of respective device. For the SiNB FET, the mobility
continues to oscillate with VBG, revealing uniformly spaced
peaks, which is an indication of the ladderlike accumulated
DOS profile of 2D subband channels.14In contrast, mobility
behavior of the SiNW FET discloses (more clearly at low gate
bias fields) the behavior of inverse-square-root singularities at
the bottoms of each 1D subband. At high gate bias, average
mobility is considerably reduced in NW devices, as more
subband channels are opened for carrier transport at higher
gate bias, due to increased intersubband scattering caused by
larger variation in effective mass of carriers in different
subband.20We confirm that higher mobility values observed
in our SiNW devices arise from enhanced intersubband
separation in ultrathin conduction channel bodies as well as
improved structural perfection and cylindrical morphology.
Therefore, quantum confinement-induced enhancement in hole
mobility justifies the recently reported higher performance in p-
SiNW FET devices.10,11
Carrier mobility can strongly be influenced by acoustic
phonon scattering. The carrier-acoustic phonon scattering rate
can be estimated employing deformation potential theory30
along with the Fermi golden rule.31For a SiNW FET of 5 nm
diameter and of EF= 10 meV, we estimate the acoustic
scattering time τac∼ 8.7 × 10−12s at 300 K. (See Supporting
Information Text 6.) Using τac∼ 8.7 × 10−12s and νF(= (2EF/
m*)1/2) ≃ 1.5 × 105m/s, one can calculate the mean free path
for carriers of light-hole mass to be
Si[110] NW FETs, the lowest two hole subbands are nearly
two-fold degenerate light-holelike20so that phonon-assisted
intersubband scattering can be neglected within these two
nearly degenerate subbands. Furthermore, considering Si
Debye energy of 55 meV32and significantly enhanced
intersubband separation (ΔEn,n+1∼ 55−75 meV) in sub-5 nm
ultrathin SiNW FETs, acoustic phonon assisted intersubband
scattering is expected to be rather minimal between the
subsequent low-lying subband channels. All these features
ac∼ 1.3 μm. In sub-5 nm
would clearly give rise to a boost in field-effect hole mobility in
our p-SiNW FETs. Our observation is in line with theoretical
predictions of enhanced hole mobility in strongly confined
NWs.13Since the carrier relaxation time is inversely propor-
tional to the DOS, relaxation time τ(E) should also reveal
oscillatory behavior because of the periodic inverse-square-root
singular enhanced DOS at the 1D subband edges of the
channel body. Although our analysis of carrier-acoustic phonon
scattering rate is macroscopic, this estimation of low scattering
rate is also in support of quantum oscillatory transport behavior
(oscillatory behavior lends to high peak performance through
unique DOS) in our sub-5 nm SiNW FETs persisting at room
temperature. Surface roughness scattering could potentially be
significant in such small nanowires. However, we expect it to be
minimal because thermal oxidation on plasma etched NWs
evidently reduces sidewall roughness.11Furthermore, as these
FETs are back-gated, the carriers would be confined away from
the possibly imperfect top oxide-Si interface. Impurity
scattering is expected to be negligible due to low doping and
reduced volume of ultrathin nanowire devices.11We suppose
the carriers are physically scattered mostly at the metallic
source and drain contacts in our junctionless devices.
Additionally, reduced carrier effective mass in an ultrathin
SiNW channel body also constitutes enhanced performance
(through reduced acoustic phonon assisted intersubband carrier
scattering) for transport within the SiNW FETs.
In summary, we have presented evidence of confinement-
induced quantum oscillatory behavior prevailing at 300 K in
drain−source current, transconductance, and field-effect
mobility characteristics of ultrathin top-down fabricated
SiNW FETs. Effects of quantum confinement on channel
conductance and transconductance are described in terms of
quantized 1D subband structures and the corresponding unique
1D DOS. Carrier mobility characteristics are shown to differ
depending on the cross sectional geometry of the channel body,
such that disparity in mobility characteristics of SiNW and
SiNB devices resemble the corresponding disparity in transfer
conductance characteristics of the drain−source current.
We conclude that strongly enhanced peak field-effect
mobility in p-SiNW FETs results from the unique 1D DOS
of inverse-square-root singularity. Ambient operation of SiNW
devices with cross sectional dimensions of sub-5 nm scales
should be understood in terms of quantum aspects of strongly
confined carriers. As such, this study would serve as a guide for
basic understanding of physical characteristics of nanoelec-
tronics devices consisting of ultrathin SiNW FETs as potential
key building blocks for future electronics devices. We believe
quantum confinement effects are a key avenue to unlock
performance and extend scalability of future Si technology as
well as foster new applications of Si devices.33
■ASSOCIATED CONTENT
*
Additional information regarding (1) carriers in confined
structures, (2) channel length- and width-dependences of
transfer characteristics, (3) intersubband separations in
cylindrical nanowires, (4) channel conductance behavior with
the gate- and channel-bias voltages, (5) subband spectroscopy,
and (6) carrier-acoustic phonon scattering rate and mean free
path. This material is available free of charge via the Internet at
http://pubs.acs.org.
S Supporting Information
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■AUTHOR INFORMATION
Corresponding Author
*E-mail: (K.S.Y.) ksyi@pusan.ac.kr; (M.J.K.) moonkim@
utdallas.edu.
■ACKNOWLEDGMENTS
This work was supported by National Science Foundation
(ECCS no. 0955027), KETI through the international
collaboration program of COSAR, the State of Texas Emerging
Technology Fund (ETF) FUSION, the World-Class University
Program (MEST through NRF (R31-10026), and by Texas
Instruments Inc., Richardson, TX. K.S.Y. acknowledges the
support from the PNU Specialization Research Grant Program
of 2011−2013.
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