Carbon nanotube memory by the self-assembly of silicon nanocrystals as charge storage nodes.

Abstract

A memory structure based on self-aligned silicon nanocrystals (Si NCs) grown over Al(2)O(3)-covered parallel-aligned carbon nanotubes (CNTs) by gas source molecular beam epitaxy is reported. Electrostatic force microscopy characterizations directly prove the charging and discharging of discrete NCs through the Al(2)O(3) layer covering the CNTs. A CNT field effect transistor based on the NC/CNT structure is fabricated and characterized, demonstrating evident memory characteristics. Direct tunneling and Fowler-Nordheim tunneling phenomena are observed at different programming/erasing voltages. Retention is demonstrated to be on the order of 10(4) s. Although there is still plenty of room to enhance the performance, the results suggest that CNT-based NC memory with diminutive CNTs and NCs could be an alternative structure to replace traditional floating gate memory.

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OLMEDO ET AL.
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September 07, 2011
C2011 American Chemical Society
Carbon Nanotube Memory by the
Self-Assembly of Silicon Nanocrystals
as Charge Storage Nodes
Mario Olmedo,†Chuan Wang,‡Koungmin Ryu,‡Huimei Zhou,†Jingjian Ren,†Ning Zhan,†Chongwu Zhou,‡
and Jianlin Liu†,*
†Department of Electrical Engineering, University of California, Riverside, California 92521, United States and‡Department of Electrical Engineering,
University of Southern California, California 90033, United States
A
ade. Most prominently, the charge trapping
memory with the CNT exposed to air has
shownlongmemorywindowstability,1robust
endurance,2sensitivity to various gases,3,4
and even resistive behavior.5Other appro-
aches such as oxide-nitride-oxide (ONO),6
nanocrystal (NC),7?11floating gate,12,13ferro-
electric,14,15and oxide16have also been im-
plemented in CNT-based memories. These
devices have shown interesting properties
suchashigh-speedprogramming/erasing16
and single electron detection.7,8Although
the use of Au NCs on an oxide-covered
CNT for memory was reported,7the devices
were fabricated based on randomly distrib-
uted CNTs. In addition, it remained unclear
whether evaporation of the Au thin film by
electron beam evaporation could give rise
to good self-alignment of Au dots on oxide-
covered CNTs and whether the NCs in
the vicinity of the CNTs would add to the
memory effect. In this article, a memory
structure using self-aligned Si NCs as the
charge trapping nodes on parallel-aligned
CNTs is demonstrated. The use of parallel-
alignedCNTswouldenablescalablefabrica-
tion, minimize the tube-to-tube junctions,
and improve the device performance. Elec-
trostatic force microscopy (EFM) measure-
ments show that the charges on the NCs
can be programmed and erased from the
CNTs through an Al2O3tunneling layer.
Furthermore, the device shows both direct
tunneling (DT) and Fowler?Nordheim (FN)
tunneling characteristics at correspond-
ing gate voltages, as well as good reten-
tion performance.
A major advantage that CNT-based de-
vices have over traditional MOSFET is its
superior scalability.17The channel width
case is approximately 5 nm.
dvances in carbon nanotube field
effect transistor (CNT?FET) memory
have been achieved in the past dec-
of a CNT is less than 2 nm, and with the
addition of discrete NCs, the channel
length for memory can also be decreased.
A characteristic of CNT-based NC memory
is that the NCs keep the charge discrete,
which can withstand non-uniformities
in the thickness of the tunneling oxide
caused by CNT roughness. Areas where
the CNT bends out of plane, causing the
tunneling oxide layer to be thinner, would
lead to easier charge leakage. If the mem-
ory would have been made using tradi-
tional poly-Si as a floating gate, it would
be prone to very short retention because
even a single leakage path caused by the
CNT roughness would drain all charges on
the continuous poly-Si gate. Moreover, NC
memory in one-dimensional channels will
have what is known as the “bottleneck”
effect,18for which as few as a single
charged NC can keep the device in an
ON or OFF state. This means that the ulti-
mate scalability of this memory is limited
onlytothesizeofasingleNC,whichinthis
*Address correspondence to
jianlin@ee.ucr.edu.
Received for review June 28, 2011
and accepted September 7, 2011.
Published online
10.1021/nn202377f
ABSTRACT A memory structure based on self-aligned silicon nanocrystals (Si NCs) grown over
Al2O3-covered parallel-aligned carbon nanotubes (CNTs) by gas source molecular beam epitaxy is
reported. Electrostatic force microscopy characterizations directly prove the charging and dischar-
gingofdiscreteNCsthroughtheAl2O3layercoveringtheCNTs.ACNTfieldeffecttransistorbasedon
theNC/CNTstructureisfabricatedandcharacterized,demonstratingevidentmemorycharacteristics.
Direct tunneling and Fowler?Nordheim tunneling phenomena are observed at different program-
ming/erasingvoltages. Retentionisdemonstrated tobeontheorder of104s.Althoughthereisstill
plenty of room to enhance the performance, the results suggest that CNT-based NC memory with
diminutive CNTs and NCs could be an alternative structure to replace traditional floating gate
memory.
KEYWORDS: carbon nanotubes.carbon nanotube memory.electrostatic force
microscopy.nanocrystal memory.nanocrystal self-assembly
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RESULTS AND DISCUSSION
The NC samples started with the growth of parallel-
aligned CNTs on a quartz substrate by the method
described in ref 19 and then transferred to a highly
boron-doped pþ-Si[100] substrate with 300 nm ther-
mally grown SiO2by thermal tape (see the Supporting
Information for experimental details). The CNT/SiO2
structure was then introduced to an atomic layer
deposition (ALD) chamber for the deposition of
11 nm Al2O3with 0.09 nm/cycle rate at 300 ?C. The
average roughness for the ALD-grown Al2O3surface
was measured to be 0.3 nm by atomic force micro-
scopy (AFM), which was slightly larger than the 0.2 nm
averageroughnessoftheSiO2only samples.Thissmall
increase in the film roughness was not found to affect
NC growth. The Al2O3-covered CNTs were then intro-
duced to a gas source molecular beam epitaxy
(GSMBE) chamber for Si NC growth. Figure 1a shows
a schematic of the structure, and Figure 1b shows an
AFM image of a typical sample, which was used for
device fabrication. The density of Si NCs is approxi-
mately 2 ? 109cm?2. For conventional NC memory
applications, where a two-dimensional cell is imple-
mented, this areal density is too low; however, it is
acceptable for a one-dimensionalmemory cell as most
of the NCs are on the apexes of the CNTs. More
evidence of Si NC alignment on parallel-aligned CNTs
covered by Al2O3is reported in the Supporting Infor-
mation. Similar preferential growth wasnoticed on the
growth of Si NCs on randomly aligned CNTs covered
with HfO2.20There it wasstudied how different growth
conditions such as growth time, oxide thickness, and
source gas flow rate influenced the NC density. There
aretworeasonsthatmaycontributetothepreferential
growth of the Si dots on the apex of the oxide-covered
CNTs. The first is related to strain in the Al2O3layer as a
result of the CNT underneath it. This strain can be
manifested as a change in surface energy, with less
energy at the surface of the oxide ridge on the CNT, or
with an increase in point defects at the areas with
strain. The second one is an effect from the trapping
areas that are formed due to the slower ALD oxide
growth on the top of the CNTs. The first reason is in-
spired by both theoretical and experimental work on
single crystal quantum dot structures on a patterned
dissimilar substrate, showing that places with less sur-
face energy will be preferential areas of nucleation of
dots.21,22The second reason is proposed because the
growth of Al2O3 by ALD uses H2O as an oxygen
precursor. This means the precursor cannot attach to
the inert CNT so the layer has to overgrow the CNT
from the sides. It has been claimed that at least 8 nm is
needed to overgrow the CNTs to completely cover
them,23which is thinner than the 11 nm used here. It
can be safely assumed yet that coverage will not be uni-
formonaCNTthathasunevencontactwiththesubstrate,
andmorepointdefectswillbepresentattheplacesalong
the CNT where it is farther from the substrate.
Todetectcharginganddischargingpropertiesofthe
NCscomparedtothesurroundingareas,EFMwasused
to map the charge distribution across the surface. The
Figure 1. (a) Schematic representation and (b) AFM image
of parallel-aligned CNTs after ALD Al2O3deposition and Si
NC growth. The image size is 2 μm with an average Si NC
height of 5 nm.
Figure2. EFMcharacterizationofCNT-basedSiNCmemory.
(a) Schematic representation of VEFM= ?3 V applied as
reading voltage. (b) EFM image of the initial state of a CNT
with Si NCs, and the inset shows the corresponding topo-
graphy. (c) Schematic representation of programming at
VP= 12 V and (d) the resulting EFM image. (e) Schematic
representation of erasing at VE= ?12 V and (f) the resulting
EFM image. The scale bar represents 500 nm.
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EFM measurement consists of a metalized Si tip first
measuring the sample topography in tapping mode.
Then the tip is raised at a constant height with respect
to topography and does a second pass over the same
area.Theelectrostaticforceoriginatedfromthesurface
will interact with the tip by changing its resonant
frequency. An attractive force lowers the frequency
and appears dark in the image, while a repulsive force
appears bright. A reading voltage (VEFM) of ?3 V was
applied at the tip (Figure 2a) during lift to be able to
repel any capacitance effect from the CNTs24and
distinguish different types of charges present at the
surface.Figure2bshowstheinitialstateEFMimageofa
CNT with NCs on top and adjacent to it, and the inset
showsits corresponding
aligned NCs are clearly observed in the topographic
image, the EFM image shows relatively even contrast
due to the lack of charges on the surface. To program
and erase the NC/CNT structure, the tip was put in
contact with the surface by using the ramp command,
which lowers the tip to the point at which the fre-
quency of the tip is nullified. This ramp command was
tunedtoalevelof5to10mVbeforethetipreachedfull
contact with the surface in order to minimize charge
leakage from the dots to the tip and vice versa. These
experiments were also carried out in a nitrogen atmo-
sphere to avoid anodic oxidation. While the tip was in
ramping mode, a voltage (VP) of 12 V was applied for
programminganda?12Vwasappliedforerasing(VE).
Inbothcases,thetotalramping timewas5s.Theramp
time defines the amount of time that the tip was inthe
ramp routine continuously. Since a 1 Hz ramp rate was
used, it meant that the tip would only ramp 5 times in
the ramping time of 5 s. This would account for a total
contact time of about 500 ms for which the tip was at
the lowest position. The results indicate the change in
charge type from a dark CNT and light QDs after
programming to bright CNT and dark QDs after eras-
ing. The reason for this change in charge state was the
large electric field that is being applied by the tip. At
VP=12V(Figure2c,d),theelectronswouldbeattracted
fromtheCNTthroughtheoxidelayerandintotheNCs.
This also happens with other NCs in the nearby area
because of the tip size and the electric field distribu-
tion on the surface.25An opposite effect occurs when
VE=?12V(Figure2e,f)wasintroducedonthetip;here
electrons were repelled and tunnel back from the NCs
to the CNT. Since the Al2O3layer outside the vicinity of
the CNTs shows little change, that is, there is no
evidence of charge injection outside of the NCs, it
can be concluded that Al2O3does not play a major
role in the storage of charges. This transfer of charge
from a channel, in this case the CNT, to the floating
gate, here the Si NCs, is similar to the charge transfer
process in a traditional MOSFET-based memory.
To further study the memory effects of the NC/CNT
structure, back-gated field effect transistor (FET)
topography. Although
devices were fabricated. The fabrication began with
the passivation of the NCs with 20 nm Al2O3, followed
byetchingdowntotheCNTsbyphotolithography and
wet etching. Source and drain contacts consisting of a
5nmTiadhesionlayerfollowedby50nmPdlayerwere
then deposited by electron beam evaporation. A sec-
ondphotolithographicstepwasperformedtoalignthe
measurement pads to the source/drain contacts, and
an additional 100 nm layer of Pd was deposited on the
resulting pattern. The channel width and length of this
device are 5 and 3 μm, respectively. Figure 3a shows
the schematic of the device, and Figure 3b shows a
scanning electron microscopy (SEM) image of the
fabricated device, which accommodated four parallel
CNTs as its channel. The linear characteristics of the
Id?Vd curves in Figure 3c indicate that the Ti/Pd
contacts used are Ohmic with a current of 862 nA at
Vds= 1 V and a grounded gate. The inset Id?Vgcurve
shows that the CNTs are p-type semiconducting, and
the current onand offratio ION/IOFFisless than 1? 103,
which is similar to other FETs made with these CNTs.26
Semiconducting characteristics in the CNTs are impor-
tantbecausethelargeonandoffratiowillfacilitatethe
characterization of the memory, including an accurate
evaluation of the threshold voltage (Vth) shift and
monitoring of the IONand IOFFcurrents as a function of
time.
The change in Vth(ΔVth) is tracked to measure the
change in memory window. The method of linear
extrapolation of Id?Vgis used to obtain Vth, that is,
Vth=Vgi?Vd/2withVgibeingthegatevoltageatwhich
Figure 3. (a) Schematic of the fabricated back gate FET
devicewithapassivationlayerof20nmontopoftheSiNCs.
(b) SEM image of the CNT-based Si NC memory device after
passivation; the scale bar indicates 1 μm. (c) Linear Id?Vd
characteristics under Vg= 10 to ?10 V with ?2 V step,
indicating that the contacts are Ohmic. The Id?Vg(inset)
characteristic suggests that the device is a p-type semi-
conducting CNT?FET.
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Ids= 0 A.27Due to the effect of the fringing electric
fields originated from the two-dimensional back gate
and one-dimensional CNT channel, as well as capaci-
tive coupling between the NCs and the back gate,28a
positive voltage is used for programming while a
negative voltage is used for erasing. In programming,
Vthshows an increase due to the presence of electrons
in the NCs, while for erasing, Vthdecreases due to the
lack of electrons or the presence of holes in the NCs.
Figure 4 shows the change in Vthwith an increase of
absolutevalueofVg.Thepulsewidthusedwas1swith
theprogrammingvoltageappliedfirst,followedbythe
erasing voltage. As the pulse amplitude increases, Vth
increases. At 20 V, there is an evident change in slope.
This was attributed to two different types of tunneling
mechanisms, that is, direct tunneling (DT) for Vg< 20 V
and Fowler?Nordheim (FN) tunneling for Vg> 20 V. At
lowVgamplitudes,chargesgothroughtheinsulatorby
DT, leading to the slow increase of ΔVth. As Vgin-
creases, the potential difference between the NCs and
CNT channel increases to make the effective tunneling
barrier width thinner, allowing more charges to tunnel
in FN tunneling mode, and as a result, ΔVthincreases
dramatically. It was calculated that FN tunneling hap-
pens when the electric field between the CNT and the
NCs is 6.4 MV/cm, which is similar to the reported
results that FN tunneling starts on other NC structures
with an electric field of 7 MV/cm.29
Retention characteristics were measured by moni-
toring Idfor 2 ? 104s, as shown in Figure 5a after the
device had been programmed and erased. Figure 5b
shows the Id?Vg curves for the fresh device, pro-
grammed device after þ30 V for 1 s, and erased device
after?30Vfor1s,indicatingevidentmemoryeffect.In
addition, the reading gate voltage can be tuned to
show the largest window for the ON and OFF state
currents. Inthis case,the readingvoltageis?2.5V.The
trade-off is that the device will experience shorter
electron retention due to the presence of the constant
negative potential on the NCs. This can be avoided if a
reading voltage of 0 V is used, although in this case,
the memory window is smaller than that of the ?2.5 V
reading. In Figure 5a, the top curve is the retention per-
formance in the programmed state while the bottom
curve is the retention performance in the erased state.
The retention curve for the programmed state has two
slopes. The first slope (ΔId/t), where t is from the initial
to7?103s,hasarapidlossofΔId/t≈?46pA/s,which
is due to the fast leakage of the stored electrons at
the higher energy levels in the NC quantum well or
shallow defect levels such as interface trap levels
between the CNTs and the surrounding oxide. The
smaller slope of ΔId/t ≈ ?1.4 pA/s for the waiting time
longer than 7 ? 103s is due to the slower leakage of
the stored charges occupying deeper energy levels
in the NC quantum well. Hole retention differs from
Figure 4. Vthchange as a function of absolute value of Vg.
A positive voltage is used for programming, while a nega-
tive voltage is used for erasing. During the programming
and erasing, the pulse width is 1 s, while the source/drain
are common.
Figure 5. (a) Retention characteristics of the CNT-based Si
NC FET memory device. Programming and erasing voltages
areVg=?30and30V,respectively.Thelinearfittingisused
to extrapolate the time when all charges are lost to be
approximately 4 ? 104s. (b) Id?Vgcurves for fresh, pro-
grammed, and erased states, showing memory effect.
The reading voltage of Vg= ?2.5 V was applied constantly
throughouttheretentionmeasurement.(c)Bandalignment
oftheCNT-basedSiNCmemorywithdifferentvaluesforthe
Al2O3Eg, electron barrier height, and hole barrier height
depending on the crystalline state of the Al2O3.
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electron retention due to a smaller slope of ΔId/t ≈
1 pA/s. This phenomenon is attributed to the higher
electron barrier from the CNT to the NCs. Figure 5c
shows the band alignment of the device structure. The
band gap (Eg) of Al2O3is 8.8 eV.30This defines an
electron barrier of 2.8 eV for electrons at the NC side,
which is indeed smaller than the electron barrier of
3.35 eV at the CNT side. It should be noted that for
amorphous Al2O3, which is closer to the film grown by
ALD,Egwasobservedtobe6.95eV.31Thismodification
shall result in an electron barrier of 2.08 eV at the Si NC
side and of 2.63 eV at the CNT side. These values
though smaller would still yield the same relationship
between the hole and electron retention results. By
extrapolatingthecurve,theretentionofthisdevicecan
be approximately 1 ? 104s when ION/IOFFratio reaches
10and4?104satthepointofcompletelossofcharge.
In contrast, the longest reported retention time for a
CNT-based memory by using the time lasted until the
ION/IOFF ratio reaches 10 is 1.5 ? 104s.16Further
extrapolation leads to a retention time of around
3 ? 104s assuming all charges are lost, which suggests
the present device has a slightly better retention.
Nevertheless, the retention is still short compared
with state-of-the-art Si-MOSFET-based floating gate
memory where the requirement is ∼3 ? 108s. This
suggests that there is plenty of room to optimize the
CNT-based memory device, such as improving the
quality of tunneling oxide.
CONCLUSIONS
A memory using Si NC floating gate on Al2O3-
covered aligned semiconducting CNTs has been de-
monstrated. EFM measurement results show that the
chargesaretransferred betweenthe CNTsandthe NCs
in the process of programming and erasing and are
kept discretely in the NCs during the retention. NC
charging characteristics exhibit a change from DT at
lower Vgto FN tunneling at higher Vg. Finally, charge
retention was measured by operating the device con-
tinuously and measuring the change in Id, for which a
moderate retention time was achieved. We believe
that, with further optimization, this technology can
enhance the scalability of NC memory. Therefore, it
may be a potential candidate to replace traditional
floating gate memory in the future.
METHODS
CNT Transfer. The parallel-aligned CNTs were grown on a
quartz substrate by the method described in ref 19. Then a
100 nm Au layer was deposited by e-beam evaporation with a
0.01 nm/srateforthe first5 nmthen a0.1 nm/sratefor therest.
A heavily boron-doped Si-pþwafer that had been covered with
300 nm thermally grown SiO2was heated to 150 ?C on a hot
plate. The thermal release tape (Nitto Denko Revalpha 3198 M
tape) was subsequently used to remove the Au/CNT film from
thequartzandtransfertotheSiO2surface.Oxygenplasmaat40
W for 10 min was then used to get rid of the tape residue, and
finally, the Au layer was etched with an Au etchant (Transene
Gold etchant TFA).
CNT-Based Si NC Memory Device Structure Growth. The CNTs on
SiO2samples were then prepared for ALD growth by introdu-
cingthemtoUVozonetreatmentfor10mintomakethesample
surface hydrophilic. The ALD sources used were aluminum
tetrachloride (AlCl4) and water (H2O). The growth was carried
out at 300 ?C under low pressure (2 ? 10?2Torr) with a 15 s
interval between each source. A nominal 11 nm Al2O3was
grown on the sample to act as the tunneling layer. The samples
were then introduced into a home-built GSMBE system, which
was subsequently pumpedto high vacuum (1 ?10?7Torr). The
sample was heated to 650 ?C, and disilane was introduced at
4 sccm for 5 min. For fabrication of the FET memory devices, a
passivationlayerof20nmAl2O3wasgrownusingthesameALD
conditions as used for the tunneling layer.
Acknowledgment. The authors thank the National Science
Foundation (DMR-0807232), and DMEA Center on Nanomater-
ials and Nanodevices (3D Electronics program), and Focused
Research Center Program (FCRP) on FENA for financial support
ofthisresearch.TheSanBernardinoCommunityCollegeDistrict
Applied Technology Training Center is also acknowledged for
providing access to their AFM measurement system.
Supporting Information Available: AFM images of NC align-
ment change with temperature and flow rate. Transient mem-
ory characteristics of the device fabricated. Retention char-
acteristics of reference sample without NCs. This material is
available free of charge via the Internet at http://pubs.acs.org.
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