Medium-scale carbon nanotube thin-film integrated circuits on flexible plastic substrates.

Abstract

The ability to form integrated circuits on flexible sheets of plastic enables attributes (for example conformal and flexible formats and lightweight and shock resistant construction) in electronic devices that are difficult or impossible to achieve with technologies that use semiconductor wafers or glass plates as substrates. Organic small-molecule and polymer-based materials represent the most widely explored types of semiconductors for such flexible circuitry. Although these materials and those that use films or nanostructures of inorganics have promise for certain applications, existing demonstrations of them in circuits on plastic indicate modest performance characteristics that might restrict the application possibilities. Here we report implementations of a comparatively high-performance carbon-based semiconductor consisting of sub-monolayer, random networks of single-walled carbon nanotubes to yield small- to medium-scale integrated digital circuits, composed of up to nearly 100 transistors on plastic substrates. Transistors in these integrated circuits have excellent properties: mobilities as high as 80 cm(2) V(-1) s(-1), subthreshold slopes as low as 140 m V dec(-1), operating voltages less than 5 V together with deterministic control over the threshold voltages, on/off ratios as high as 10(5), switching speeds in the kilohertz range even for coarse (approximately 100-microm) device geometries, and good mechanical flexibility-all with levels of uniformity and reproducibility that enable high-yield fabrication of integrated circuits. Theoretical calculations, in contexts ranging from heterogeneous percolative transport through the networks to compact models for the transistors to circuit level simulations, provide quantitative and predictive understanding of these systems. Taken together, these results suggest that sub-monolayer films of single-walled carbon nanotubes are attractive materials for flexible integrated circuits, with many potential areas of application in consumer and other areas of electronics.

Full text

Page 1

Purdue University
Purdue e-Pubs
Birck and NCN PublicationsBirck Nanotechnology Center
7-24-2008
Medium-scale carbon nanotube thin-film
integrated circuits on flexible plastic substrates
Qing Cao
Univ Illinois, Dept Chem
Hoon-sik Kim
Univ Illinois, Dept Mat Sci & Engn
Ninad Pimparkar
Purdue Univ, Sch Elect & Comp Engn, Network Computat Nanotechnol, pimparkar@gmail.com
Jaydeep Kulkarni
Purdue Univ, Sch Elect & Comp Engn, Network Computat Nanotechnol, jaydeep@purdue.edu
Congjun Wang
Univ Illinois, Dept Mat Sci & Engn
See next page for additional authors
This document has been made available through Purdue e-Pubs, a service of the Purdue University Libraries. Please contact epubs@purdue.edu for
additional information.
Cao, Qing; Kim, Hoon-sik; Pimparkar, Ninad; Kulkarni, Jaydeep; Wang, Congjun; Shim, Moonsub; Roy, Kaushik; Alam,
Muhammad A.; and Rogers, John A., "Medium-scale carbon nanotube thin-film integrated circuits on flexible plastic substrates"
(2008).Birck and NCN Publications.Paper 152.
http://docs.lib.purdue.edu/nanopub/152

Page 2

Authors
Qing Cao, Hoon-sik Kim, Ninad Pimparkar, Jaydeep Kulkarni, Congjun Wang, Moonsub Shim, Kaushik
Roy, Muhammad A. Alam, and John A. Rogers
This article is available at Purdue e-Pubs:http://docs.lib.purdue.edu/nanopub/152

Page 3

LETTERS
Medium-scale carbon nanotube thin-film integrated
circuits on flexible plastic substrates
QingCao1,Hoon-sikKim2,NinadPimparkar7,JaydeepP.Kulkarni7,CongjunWang2,MoonsubShim2,KaushikRoy7,
Muhammad A. Alam7& John A. Rogers1–6
The ability to form integrated circuits on flexible sheets of plastic
enablesattributes(forexampleconformalandflexibleformatsand
lightweight and shock resistant construction) in electronic devices
thataredifficultorimpossibletoachievewithtechnologiesthatuse
semiconductorwafersorglassplatesassubstrates1. Organicsmall-
molecule and polymer-based materials represent the most widely
explored types of semiconductors for such flexible circuitry2.
Althoughthesematerialsandthosethatusefilmsornanostructures
of inorganics have promise for certain applications, existing
demonstrations of them in circuits on plastic indicate modest per-
formance characteristics that might restrict the application pos-
sibilities. Here we report implementations of a comparatively
high-performance carbon-based semiconductor consisting of
sub-monolayer, random networks of single-walled carbon nano-
tubes to yield small- to medium-scale integrated digital circuits,
composed of up to nearly 100 transistors on plastic substrates.
Transistors in these integrated circuits have excellent properties:
mobilities as high as 80cm2V21s21, subthreshold slopes as low as
140mVdec21,operatingvoltageslessthan5Vtogetherwithdeter-
ministiccontroloverthethresholdvoltages,on/offratiosashighas
105, switching speeds in the kilohertz range even for coarse ( 100-
mm) device geometries, and good mechanical flexibility—all with
levelsofuniformityandreproducibilitythatenablehigh-yieldfab-
ricationofintegrated circuits.Theoreticalcalculations,incontexts
rangingfromheterogeneouspercolativetransportthroughthenet-
workstocompactmodelsforthetransistorstocircuitlevelsimula-
tions, provide quantitative and predictive understanding of these
systems. Taken together, these results suggest that sub-monolayer
filmsofsingle-walledcarbonnanotubesareattractivematerialsfor
flexible integrated circuits, with many potential areas of applica-
tion in consumer and other areas of electronics.
Efforts to develop polymer and small-molecule semiconductors
for electronics have yielded several impressive demonstrations,
including integrated circuits with more than 1000 transistors3, flex-
ible displays3,4, sensor sheets5and other systems6,7. In all cases, how-
ever,thefield-effectmobilities ofthetransistorsaremodest:typically
,1cm2V21s21for isolated devices8,9and ,0.05cm2V21s21in
integrated circuits3–7. Although these properties are sufficient for
electrophoretic displays and certain other applications, improve-
ments in the materials would expand the possibilities1. Separately,
for any given application, increases in mobility relax the require-
ments on critical feature sizes in the circuits (for example transistor
channel lengths) and tolerances on their multilevel registration,
which can be exploited to reduce the cost of the plastic substrates
and patterning systems to achieve roll-to-roll fabrication by dry
printing10or ink-jet printing11.
Recently developed carbon-based semiconducting nanomaterials,
especially single-walled carbon nanotubes (SWNTs), might provide
an opportunity to achieve extremely high intrinsic mobilities, high
current-carryingcapacitiesandexceptionalmechanical/opticalchar-
acteristics, in bendable formats on plastic substrates12. Although iso-
lated SWNTs are not relevant to the applications contemplated here,
recent work shows that sub-monolayer random networks13–16or
aligned arrays17,18of SWNTs can serve as thin-film semiconductors
which, in the best cases, inherit the exceptional properties of the
tubes, for example device mobilities up to ,2,500cm2V21s21, on-
state currents above several milliamperes, and cut-off frequencies
above 1GHz for devices on plastic. The network geometry is of
particular interest for flexible electronics because it can be easily
achieved by printing SWNTs from solution suspensions19. The pre-
sentworkdemonstratesimplementationsofSWNTnetworksinflex-
ible integrated circuits on plastic that have attractive characteristics,
togetherwithcorrespondingtheoreticalmodelsandsimulationtools
that capture all of the key aspects.
The system layouts (Fig. 1a) exploit architectures similar to those
in established silicon integrated circuits. A thin (50-mm) sheet of
polyimide serves as the substrate. Random networks of SWNTs
grown by chemical vapour deposition and subsequently transfer
printed onto the polyimide form the semiconductor layer17. Source
anddrain(S–D)electrodesofgoldserveaslow-resistancecontactsto
thesenetworks,asdeterminedbyscalingstudies(SupplementaryFig.
1). Although roughly one-third of the SWNTs are metallic, purely
metallictransportpathwaysbetweentheS–Delectrodescanbeelimi-
nated by suitably engineering the average tube lengths and the net-
work layouts: for the present purposes, we used soft lithography and
reactive-ion etching to cut fine lines into the networks. The resulting
network strips are oriented along the overall direction of transport,
with widths designed to reduce the probability of metallic pathways
below a practical level without significantly reducing the effective
thin-film mobility of the network.
Figure 1b shows a scanning electron micrograph of a region of an
integrated circuit just beforedeposition ofthegatedielectric. Amag-
nifiedviewofapartoftheSWNTnetworkinthechannelofoneofthe
devices (Fig. 1c; the S–D electrodes are to the right and left, outside
the field of view) reveals narrow, dark horizontal lines, correspond-
ing to the etched regions. The critically important role of these fea-
tures in determining the electrical characteristics can be quantified
through first-principles modelling studies that consider percolative
transport through sticks with average lengths and layouts (for
example etched lines, densities of SWNTs and so on) corresponding
to experiment20. Fig. 1d shows the distribution of current flow in a
typical case, in which the colour indicates the current density in the
1Department of Chemistry,2Department of Materials Science and Engineering,3Department of Electrical and Computer Engineering,4Department of Mechanical Science and
Engineering,5Frederick-Seitz Materials Research Laboratory,6Beckman Institute for Advanced Science and Technology, University of Illinois at Urbana-Champaign, Urbana, Illinois
61801, USA.7School of Electrical and Computer Engineering, Network for Computational Nanotechnology, Purdue University, West Lafayette, Indiana 47907, USA.
Vol 454|24 July 2008|doi:10.1038/nature07110
495
©2008 Macmillan Publishers Limited. All rights reserved

Page 4

on-state of the device. In addition to providing guidance on optimal
design (Fig. 2a), these simulations reveal that networks with this
geometry and coverage (,0.6%) distribute current evenly, thereby
servingasaneffectivefilmfortransport.Atypicaldeviceincorporates
,16,000 individual SWNTs. The circuits are completed in top-gate
configurations by deposition and patterning of high-capacitance,
hysteresis-free dielectrics enabled by low operating voltages
(,40nm of hafnium dioxide) directly on the tubes, followed by gate
metallization and the addition of vias and interconnects. Figure 1e
shows a representative system, complete with arrays of isolated
enhancement-mode(lowerrightregion)anddepletion-mode(lower
middle region) transistors, various logic gates (lower left part), and
twofour-bitrowdecoderseachtwentylogicgatesinsize(middleand
upper parts). Fabrication details are further described in the
Methods.
Figure 2 summarizes measurements on individual transistors.
Figure 2a illustrates the predicted and measured influences of the
geometry of the etched lines described above on devices with coarse
dimensions (that is, channel lengths LC5100mm), selected to be
compatible with established low-cost patterning techniques such as
screen printing21, and with sufficiently high densities of SWNTs to
achieve good performance and uniformity as a thin-film semi-
conductor. For widths of ,5mm, the etched lines increase the on/
off ratios by up to four orders of magnitude, while reducing the
transconductances(gm)byonly,40%.Figure2b,cshowscharacter-
istics of transistors with this geometry, illustrating well-behaved res-
ponses with minimal hysteresis and with excellent channel-width-
normalizedtransconductances(ashighas0.15mSmm21andtypically
0.12mSmm21for LC$50mm, which corresponds to an estimated
cut-off frequency of .100kHz), device mobilities (meff; as high as
,80cm2V21s21and typically ,70cm2V21s21as calculated using
standard models of metal–oxide–semiconductor field-effect transis-
tors with measured gate capacitances (Supplementary Fig. 2), for
both the linear and the saturation regimes), and subthreshold swings
(S; as low as 140mVdec21and typically ,200mVdec21).
The transconductances and the subthreshold behaviours, in par-
ticular, exceed those that have been demonstrated in flexible inte-
grated circuits on plastic with organic thin-film semiconductors
(gm,0.02mSmm21for LC<50mm, S.140mVdec21)22,23or with
siliconnanowires(gm,0.01mSmm21
S.280mVdec21)24, and are competitive with the best reports of
p-channel single-crystalline silicon ribbons (gm<0.25mSmm21for
LC550mm,S<230mVdec21)25.Underlow-to-moderatebiascon-
ditions, the on/off ratios can be as high as 105(Fig. 2f and
Supplementary Fig. 3a), and typically ,103, for transistors with this
geometry. The inset in Fig. 2b and Supplementary Fig. 4a show a
decrease in the on/off ratio with increasing drain–source voltage
(VDS), which is due primarily to the slightly ambipolar nature of
the device operation. These ratios also decrease with LC
(Supplementary Fig. 1b). The favourable d.c. properties of long-
channel devices can be achieved at short LCs, for improved operating
speeds, either by use of correspondingly shorter SWNTs and nar-
rower etched stripes, as suggested by modelling results, or by using
pre-enriched semiconducting SWNTs26.
The threshold voltage (VT) can be controlled by using gate metals
with different work functions, because the high-capacitance gate
dielectrics reduce the relative contribution of voltage across the
dielectrictoVT(ref.27).Forexample,replacinggoldwithaluminium
as the gate metal shifts VTby 2(0.6–0.8)V, thereby changing the
device operation from depletion mode to enhancement mode
(Fig.2b).Systematicbendingtestsofindividualdevicesandinverters
showed no significant change in device performance during inward
or outward bending to radii as small as ,5mm (Fig. 2d).
Collectively, these properties are as good as or better than those of
previously reported devices based on SWNT random networks, in
spite of the moderate decreases in gmassociated with the etching
procedures. Transistors that use dense, perfectly aligned arrays of
SWNTs have improved performance, that is, device mobility up to
2,500cm2V21s21, but these layouts cannot be formed readily with
solution deposition techniques17. As such, they are not relevant for
the type of printed, flexible electronics applications contemplated
here.
forLC<50mm,
PI substrate
PU
PI from PAA
S–D electrodes
Gate
Interconnect
SWNT
Via
100 µm
5 mm
e
d
cb
a
5 µm
5 µm
Figure 1 | Illustration, scanning electron microscope images, theoretical
modellingresultsandphotographsofflexibleSWNTintegratedcircuitson
plastic. a, Cross-sectional diagram of a SWNT PMOS inverter on a PI
substrate.PI,polyimide;PU,polyurethane;PAA,polyamicacid;Vdd;Vdd,
common power supply voltage; Vout;Vout, output voltage; Vin;Vin,
input voltage; GND, common ground. b, Scanning electron microscope
image of part of the SWNT circuit, made before deposition of the gate
dielectric, gate or gate-level interconnects. The S–D electrodes (gold) and
substrates (brown) had been colourized to highlight the SWNT network
strips(blackandgrey)thatformthesemiconductor.c,Magnifiedviewofthe
network strips corresponding to a region of the device channel highlighted
with the white box in b. d, Theoretical modelling results for the normalized
currentdistribution intheon-stateofthedevice(viewasin c),wherecolour
indicates current density (yellow, high; red, medium; blue, low).
e, Photograph of a collection of SWNT transistors and circuits on a thin
sheet of plastic (PI).
LETTERS
NATURE|Vol 454|24 July 2008
496
©2008 Macmillan Publishers Limited. All rights reserved

Page 5

Foruseinintegratedcircuits,theyieldsandperformanceuniform-
ity of the transistors are critically important. We examined these
aspects through measurements on more than 100 devices (Fig. 2e, f
and Supplementary Fig. 5). The results show standard deviations of
,20% for the normalized on-state current (Ion) and ,0.05V for VT.
The former result is quantitatively in agreement with percolation
theory, illustrated also in Fig. 2e. Although on/off ratios vary by
roughly two orders of magnitude, most of the values are .103. The
distribution(Fig.2f)indicatesnocorrelationwithVT(suggestingthe
importance ofextrinsic doping effects onSWNTs28),andhas awidth
which is much larger than that predicted by percolation models
(Fig. 2f, inset) that do not explicitly include effects of S–D contacts.
These results strongly indicate that the variation in on/off ratio
results from electron conduction caused by tunnelling through the
Schottky barriers at the S–D contacts (Fig. 2f, inset)29. Although
unnecessary for the circuits reported here, doping techniques similar
to those demonstrated in single-SWNT devices can be used to sup-
press the ambipolar behaviour and improve on/off ratio uniform-
ity30. Such doping methods could also help to eliminate decreases in
on/off ratio with increasing VDS, as mentioned previously and illu-
strated in Fig. 2b and Supplementary Fig. 4a.
We find that standard models for silicon device technologies can
capture macroscopic device behaviours. Figure 2b, c illustrates the
level of agreement that can be achieved with a level-3 p-channel
metal–oxide–semiconductor (PMOS) SPICE (simulation program
for integrated circuits emphasis) model that uses a parallelly con-
nected exponential current source controlled by both gate voltage
and VDSto mimic the electron tunnelling current. This level of com-
patibility with established simulation tools allows the use of existing
sophisticatedcomputer-aideddesignplatformsdevelopedforsilicon
integrated circuits.
As the first step towards large-scale integration, we modelled and
then built ‘universal’ logic gates. Figure 3a shows a circuit diagram
of a PMOS inverter with enhancement load. The inverter exhibits
well-defined static voltage transfer characteristics, consistent with
simulation, at a supply voltage of 25V (Fig. 3b). The rise in output
voltage with increasing positive input voltage is due to the ambipo-
lar behaviour of the driving transistor. Maximum voltage gains of
,4, together with good noise immunity with a transition-region
width of ,0.8V and a logic swing of .3V are achieved, indicating
that the inverter can be used to switch subsequent logic gates with-
out losing logic integrity. Measuring their a.c. responses generated a
106
1.0
abc
def
–15
–25
–20
–15
–10
–5
0
Gold
Aluminium
10–5
–2 –1012
–20–1–2
VDS (V)
–3 –4
105
104
103
102
1102
gmn/gmn
VT – VT (V)
–5–1012
10–6
10–7
10–8
IDS (µA)
IDS (µA)
–IDS (µA)
VGS (V)
VGS (V)
–10
–5
0
0.8
0.6
0.4
0.2
0.0
gm/gm0
gm/gm0
G/G0
1 10100
Number of transistors
WS (µm)
Ion/Ioff
104
102
100
1.1
15
10
5
00.5
1.0
Ion/Ion
Ion/Ioff
1.5
105
104
103
0.10
0.00
–0.10
5
Number of devices
3
1
1.0
0.9
1.1
1.0
0.9
55 10
Radius (mm)
10
∞
Ion/Ioff
Figure 2 | Electrical properties of thin-film transistors that use SWNT
network strips for the semiconductor, on thin plastic substrates. a, The
measured (filled) and simulated (open) influence of the width of the strips
(WS) on the on/off ratio (Ion/Ioff; black) and normalized transconductance
(gm/gm0, where gm0represents the response without strips; blue) of
transistorswithchannellengthsof100mm.Errorbarsrepresents.d.ofn56
thin-film transistors. b, Measured (solid) and simulated (dashed) VGS–IDS
characteristics of depletion-mode (blue) and enhancement-mode (black)
SWNT thin-film transistors whose channel widths are 200mm and whose
channel lengths are 100mm. VDS521V; IDS, drain–source current; VGS,
gate–source voltage. Inset, VGS–IDScurve of the enhancement-mode device
plotted on a logarithmic scale, with VDS520.5V (navy), 22V (green),
25V (magenta). c, Measured (black) and simulated (red) VDS–IDS
characteristics of an enhancement-mode thin-film transistor (VGSchanged
from 22V to 2V in steps of 0.5V). d, Plots of gm/gm0for a thin-film
transistorandG/G0(normalizedvoltagegain)foraninverterasfunctionsof
bend radius (gm0and G0denote the responses in the unbent state).
e, Histogram of Ion(measured at VDS520.2V;?I Ion, averaged on-state
current) with superimposed gaussian fitting for measured (dashed black)
and simulated (dashed red) results. f, Two-dimensional histogram showing
the correlation between the Ion/Ioff(measured at VDS520.2V) and
threshold voltage distributions (?V VT, averaged threshold voltage). Inset,
correlation between Ion/Ioffand normalized n-branch transconductance
(? g gmn,averagedn-branchtransconductance).Thedashedbluelinedepictsthe
result of a linear fit. The hatched red area shows the distribution of Ion/Ioff
predicted by percolation models that do not explicitly account for the
influence of source–drain contacts.
NATURE|Vol 454|24 July 2008
LETTERS
497
©2008 Macmillan Publishers Limited. All rights reserved

Page 6

Bode magnitude plot closely resembling the characteristics of low-
pass amplifiers, with operation in the kilohertz range even for
devices with long channels (LC<100mm) and significant channel-
width-normalized overlap capacitance (,40fFmm21; Fig. 3c). The
ability to achieve switching speeds in the kilohertz range with device
geometries that are compatible with techniques such as screen print-
ing is important for the potential use of such SWNT networks in
low-cost, printed electronics21. By adding another driving transistor
to the inverter, either in parallel with the pull-down transistor to
incorporate OR logic (Fig. 3d, e) or in series to incorporate AND
logic (Fig. 3g, h), it is possible to construct NOR and NAND logic
gates, respectively. The output characteristics and simulation results
are presented in Fig. 3f, i. Voltage amplification is observed in all
cases.
All of these experimental and computational components can be
used together to yield SWNT-based digital circuits (Fig. 4a). The
largestcircuitinthischipisafour-bitrowdecoder(Fig.4b),designed
using modelling tools and measured characteristics of stand-alone
logic gates. This circuit incorporates 88 transistors, in four inverters
andaNORarray,withtheoutputoftheinverterservingasoneofthe
inputs for the NOR gate. The circuit diagram (Fig. 4c) is configured
such that any given set of inputs only give one logic-‘1’ output. The
input–output characteristics of the decoder are shown in Fig. 4d and
Supplementary Fig. 6, which demonstrates its ability to decode a
binary-encoded input of four data bits into sixteen individual data
output lines, at frequencies in the kilohertz range. These results sug-
gest that SWNT networks can form the basis for a potentially inter-
esting and scalable alternative to conventional organic or other
classes of semiconductors for flexible integrated circuitry applica-
tions.Thedevelopmentofoptimizedmaterialsandsolution-printing
techniques for fabricating SWNT-based integrated circuits that
achieve the performance levels reported here, together with further
exploration of circuit- and systems-level implementation, represent
some directions for future work.
a
d
ghi
ef
bc
0
Vdd
Vdd
Vdd
Vin
Vout
Vout
Vout
VA
VB
VA
VB
0
–4
5
0
–5
–10
–15
0.4
Voltage (V)
0.0
01
t (ms)
2
–0.4
–20
0
–2
(0,0)1
(0,0)1
(1,1)0
(1,0)1 (0,1)1
(1,1)0
(1,0)0 (0,1)0
–4
–6
Time
Time
10100
Frequency (Hz)
1,00010,000
Vin
Vout
–2
0
–2
–4
–4–202
Vin (V)
VA
VB
Vout
Sim
VA
VB
Vout
Sim
Vout (V)
Vout (V)
0
–2
–4
–6
Vout (V)
4
Gain
Gain (dB)
0
0
Figure 3 | Circuit diagram, optical micrographs, output–input
characteristics and circuit simulation results for different logic gates.
a–c, Inverter. d–f, NOR gate. g–i, NAND gate. We adopt a negative logic
system. The Vddapplied to these logic gates is 25V relative to GND. The
logic-‘0’ and -‘1’ input signals of two terminals (VA;VA and VB;VB) of
the NOR and NAND gates are driven by 0V and 25V, respectively. The
logic-‘0’ and -‘1’ outputs of the NOR gate are 2(0.88–1.39)V and –3.85V,
respectively.Thelogic-‘0’and-‘1’outputsoftheNANDgateare–1.47Vand
2(4.31–4.68)V, respectively. In b: black, Vout; blue, gain. In f and i, any
specific combination of input–output signals is indicated as (logic address
level inputs)logic address level ouput, and the timescales on the x axes are
omittedbecausedatacollectioninvolvedtheswitchingofvoltagesettingsby
hand.Inb,fandi,dashedredlinesrepresentcircuitsimulationresults.Scale
bars in e and h, 100mm.
LETTERS
NATURE|Vol 454|24 July 2008
498
©2008 Macmillan Publishers Limited. All rights reserved

Page 7

METHODS SUMMARY
TheprocessflowforfabricatingSWNTintegratedcircuitsonplasticsisdepicted
in Supplementary Fig. 8. SWNTs were synthesized by chemical vapour depos-
ition on silicon dioxide–silicon wafers and then etched into strips using an
experimentally simple, optical soft lithography technique. Standard photolitho-
graphy, electron-beam evaporation, gold wet chemical etching and oxygen
plasma etching were used to pattern S–D electrodes and isolate each device.
We then used a film of polyamic acid to encapsulate predefined S–D electrodes
and SWNT networks on the growth wafers for transfer to a polyimide substrate
coated with liquid polyurethane. Subsequent curing of the liquid polyurethane
and polyamic acid completed the transfer process. Metal gates were defined on
top of a high-capacitance dielectric (,40-nm) layer of hafnium dioxide. Vias
andwindowsforprobingwereopenedbywetetching(dippedintoconcentrated
hydrofluoric acid aqueous solution) through patterned photoresist. Last,
another level of interconnect metallization formed local interconnections
defined previously with the gate and source–drain metal layers. All electrical
measurementswerecarriedoutinairusingasemiconductorparameteranalyser
(Agilent, 4155C). Alternating-current input was provided by a function gen-
erator (GW Instek, GFG-8219A) and output was read using a standard oscil-
loscope (Tektronix, TDS 3012B). The stick percolation simulations involved
finite-size,first-principlestwo-dimensionalnumericalmodelsbasedongeneral-
ized heterogeneous random network theory. Device and circuit simulation used
the commercial software package HSPICE (Synopsis).
Full Methods and any associated references are available in the online version of
the paper at www.nature.com/nature.
Received 29 January; accepted 20 May 2008.
1. Reuss, R. H.etal. Macroelectronics: Perspectives on technology andapplications.
Proc. IEEE 93, 1239–1256 (2005).
2.Forrest,S.R.Thepathtoubiquitousandlow-costorganicelectronicapplianceson
plastic. Nature 428, 911–918 (2004).
Gelinck, G. H. et al. Flexible active-matrix displays and shift registers based on
solution-processed organic transistors. Nature Mater. 3, 106–110 (2004).
Rogers, J. A. et al. Paper-like electronic displays: Large-area rubber-stamped
plastic sheets of electronics and microencapsulated electrophoretic inks. Proc.
Natl Acad. Sci. USA 98, 4835–4840 (2001).
Someya, T. et al. Conformable, flexible, large-area networks of pressure and
thermal sensors with organic transistor active matrixes. Proc. Natl Acad. Sci. USA
102, 12321–12325 (2005).
Sekitani, T. et al. A large-area wireless power-transmission sheet using
printed organic transistors and plastic MEMS switches. Nature Mater. 6, 413–417
(2007).
Crone, B. et al. Large-scale complementary integrated circuits based on organic
transistors. Nature 403, 521–523 (2000).
Singh, T. B. & Sariciftci, N. S. Progress in plastic electronics devices. Annu. Rev.
Mater. Res. 36, 199–230 (2006).
Briseno, A. L.etal.Patterningorganic single-crystal transistor arrays. Nature 444,
913–917 (2006).
10. Blanchet, G. B., Loo, Y. L., Rogers, J. A., Gao, F. & Fincher, C. R. Large area, high
resolution,dryprintingofconductingpolymersfororganicelectronics. Appl.Phys.
Lett. 82, 463–465 (2003).
11.Sirringhaus, H. et al. High-resolution inkjet printing of all-polymer transistor
circuits. Science 290, 2123–2126 (2000).
12. Avouris, P., Chen, Z. H. & Perebeinos, V. Carbon-based electronics. Nature
Nanotechnol. 2, 605–615 (2007).
13. Bradley, K., Gabriel, J. C. P. & Gruner, G. Flexible nanotube electronics. Nano Lett.
3, 1353–1355 (2003).
14. Zhou, Y. X. et al. p-channel, n-channel thin film transistors and p-n diodes based
on single wall carbon nanotube networks. Nano Lett. 4, 2031–2035 (2004).
15. Snow, E. S., Campbell, P. M., Ancona, M. G. & Novak, J. P. High-mobility carbon-
nanotube thin-film transistors on a polymeric substrate. Appl. Phys. Lett. 86,
033105 (2005).
3.
4.
5.
6.
7.
8.
9.
Vdd
GND
Time
Output (V)
Input (V)
MSB SB
TB LSB
0
LSB
TB
SB
MSB
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
–4
0
–4
0
–4
0
–2
0
–2
0
–2
0
–2
0
–2
0
–2
0
–2
0
–2
0
–2
0
–2
0
–2
0
–2
0
–2
0
–2
0
–2
0
–2
0
–4
–4
–2
–3
–2
–1
0
0
01
t (ms)
2
Vin (V)
Vout (V)
2 mm
a
b
c
d
5 mm
Figure 4 | Medium-scale integrated circuits based on SWNT network
strips, on a thin plastic substrate. a, Optical image of a flexible SWNT
integrated circuit chip bonded to a curved surface. b, Optical micrograph
andc,circuitdiagramofafour-bitrowdecoderwithsixteenoutputs(0–15).
The bits are designated as most significant bit (MSB), second bit (SB), third
bit (TB)andleastsignificantbit (LSB). TheVddappliedwas 25V relativeto
GND. d, Characteristics of the four-bit decoder. In descending order, the
first four traces are inputs, labelled LSB, TB, SB and MSB on the right-hand
side;theremainingtraces,labelled‘0’to‘15’,showtheoutputvoltagesofthe
sixteenoutputs.Inset,measured(blue)andSPICE-simulated(red)dynamic
response of one output line under a square-wave input pulse (black) at a
clock frequency of 1kHz.
NATURE|Vol 454|24 July 2008
LETTERS
499
©2008 Macmillan Publishers Limited. All rights reserved

Page 8

16. Seidel, R. et al. High-current nanotube transistors. Nano Lett. 4, 831–834 (2004).
17. Kang, S. J. et al. High-performance electronics using dense, perfectly aligned
arrays of single-walled carbon nanotubes. Nature Nanotechnol. 2, 230–236
(2007).
18. Chimot, N. et al. Gigahertz frequency flexible carbon nanotube transistors. Appl.
Phys. Lett. 91, 153111 (2007).
19. Beecher, P. et al. Ink-jet printing of carbon nanotube thin film transistors. J. Appl.
Phys. 102, 043710 (2007).
20. Kocabas, C. et al. Experimental and theoretical studies of transport through large
scale, partially aligned arrays of single-walled carbon nanotubes in thin film type
transistors. Nano Lett. 7, 1195–1202 (2007).
21. Chason,M.,Brazis,P.W.,Zhang,H.,Kalyanasundaram,K.&Gamota,D.R.Printed
organic semiconducting devices. Proc. IEEE 93, 1348–1356 (2005).
22. Klauk, H., Zschieschang, U., Pflaum, J. & Halik, M. Ultralow-power organic
complementary circuits. Nature 445, 745–748 (2007).
23. Yoon, M. H., Yan, H., Facchetti, A. & Marks, T. J. Low-voltage organic field-effect
transistors and inverters enabled by ultrathin cross-linked polymers as gate
dielectrics. J. Am. Chem. Soc. 127, 10388–10395 (2005).
24. Duan, X. F. et al. High-performance thin-film transistors using semiconductor
nanowires and nanoribbons. Nature 425, 274–278 (2003).
25. Kim, D. H. et al. Complementary logic gates and ring oscillators on plastic
substrates by use of printed ribbons of single-crystalline silicon. IEEE Trans.
Electron Devices 29, 73–76 (2008).
26. Arnold,M.S.,Green,A.A.,Hulvat,J.F.,Stupp,S.I.&Hersam,M.C.Sortingcarbon
nanotubes by electronic structure using density differentiation. Nature
Nanotechnol. 1, 60–65 (2006).
27. Chen, Z. H. et al. An integrated logic circuit assembled on a single carbon
nanotube. Science 311, 1735 (2006).
28. Shim, M., Ozel, T., Gaur, A. & Wang, C. J. Insights on charge transfer doping and
intrinsic phonon line shape of carbon nanotubes by simple polymer adsorption. J.
Am. Chem. Soc. 128, 7522–7530 (2006).
29. Javey, A., Guo, J., Wang, Q., Lundstrom, M. & Dai, H. J. Ballistic carbon nanotube
field-effect transistors. Nature 424, 654–657 (2003).
30. Chen, J., Klinke, C., Afzali, A. & Avouris, P. Self-aligned carbon nanotube
transistors with charge transfer doping. Appl. Phys. Lett. 86, 123108 (2005).
Supplementary Information is linked to the online version of the paper at
www.nature.com/nature.
AcknowledgementsWethankT.Banks,K.ColravyandD.Sieversforhelpwiththe
processing.ThismaterialisbaseduponworksupportedbytheUSNationalScience
Foundation (NIRT-0403489), the US Department of Energy
(DE-FG02-07ER46471), Motorola, Inc., the Frederick-Seitz Materials Research
Laboratory and the Center for Microanalysis of Materials (DE-FG02-07ER46453
and DE-FG02-07ER46471) at the University of Illinois. Q.C. acknowledges
fellowship support from the Department of Chemistry at the University of Illinois.
N.P., J.P.K., M.A. and K.R. acknowledge support from the Network for
Computational Nanotechnology, which is supported by the National Science
Foundation under cooperative agreement EEC-0634750. J.P.K. acknowledges
fellowship support from the Intel Foundation.
Author Contributions Q.C., H.K. and J.A.R. designed the experiments. Q.C., H.K.
andC.W.performedtheexperiments.Q.C.,N.P.,J.P.K.,M.S.,K.R.,M.A.A.andJ.A.R.
analysed the data. Q.C. and J.A.R. wrote the paper.
Author Information Reprints and permissions information is available at
www.nature.com/reprints. Correspondence and requests for materials should be
addressed to J.A.R. (jrogers@uiuc.edu).
LETTERS
NATURE|Vol 454|24 July 2008
500
©2008 Macmillan Publishers Limited. All rights reserved

Page 9

METHODS
Synthesis of SWNT networks. SWNT random networks were grown by chem-
ical vapour deposition on silicon wafers with 100-nm-thick layers of thermal
oxide. The process began with cleaning the SiO2–Si wafer with piranha solution
(a 3:1 volumetric mixture of concentrated sulphuric acid to 30% hydrogen
peroxide solution). This process not only removed organic contaminants but
also hydroxylated the re-oxidized SiO2surface, making it extremely hydrophilic
to enable uniform deposition of catalyst31. This catalyst consisted of ferritin
(Aldrich; diluted with de-ionized water at a volumetric ratio of 1:20 to control
thedensityofcatalyst)depositedontotheSiO2–Sisurfacebyaddingmethanol32.
Thewafer was thenheated to800uC in a quartztube tooxidize ferritin intoiron
oxide nanoparticles. After it had cooled down to room temperature, the quartz
tube was flushed with a high flow of argon gas (1,500s.c.c.m.) for cleaning and
then heated up to 925uC in hydrogen atmosphere (120s.c.c.m.), which reduced
iron oxide to iron. After the temperature had reached 925uC, methane
(1,500s.c.c.m.) was released into the quartz tube as a carbon source while main-
taining the hydrogen flow. Growth was terminated after 20min, and the cham-
ber was then cooled in hydrogen and argon flow. The density of the SWNT
networks formed in this fashion was controlled by the dilution ratio of the
ferritin solution, leaving the other aspects of the growth and processing
unchanged.
Cutting strips into the SWNT networks with phase-shift lithography and
reactive-ion etching. Elastomeric phase masks with depths of 1.8mm, widths
of 5mm andperiodicities of10mm werefabricatedfrom relief structures defined
by lithography and anisotropic etching through a casting and curing proced-
ure33.AZ5214photoresist,dilutedwithAZ1500thinnerina1:1volumetricratio,
was spin-cast onto the SiO2–Si wafer with SWNT networks at 5,000 r.p.m. and
then bakedat 95uC for 1min toafford a flat and solid 300-nm-thick photoresist
layer.AftercleaningthesurfaceofphasemaskwithScotchTape,weplaceditinto
conformalcontact with the photoresist layer, floodexposedthe resistby shining
the i-line (365-nm)output of a mercury ultraviolet lamp throughthe mask,and
then removed the mask. The SiO2–Si substrate was then baked at 112uC for
another minute, followed by a flood exposure of ultraviolet light. Development
in AZ MIF327 developer for 40s created a regular array of submicrometre-wide
spacings in the photoresist layer, with 5-mm periodicity. Photoresist strips of
5-mm width could also be generated by conventional photolithography with
much wider spacings (,5mm). Although large spacings lead to a reduction in
effective channel width and an increase in parasitic capacitance, we used this
techniqueinsteadofphase-shiftlithographyinfabricatingthetransistorsusedin
thedecodercircuitsbecauseconventionalphotolithographyiseasiertoperform.
We next used oxygen reactive-ion etching (200mtorr, 20s.c.c.m., O2flow, 100-
W radio frequency power) to remove the exposed SWNTs. Last, the photoresist
layer was removed by soaking in acetone for 1h. Successfully using optical soft
lithography to pattern the only sub-10-mm features in our circuits suggests the
potential to use low-cost, low-resolution printing-like processes to define all
features in the circuits34.
S–D patterning and device isolation. A gold film (30nm) was deposited by
electron-beam evaporation (TemescalBJD 1800;basepressure of 331026torr)
ontoaSiO2-Sisubstratewithpredefinednanotubestrips.Wethenusedstandard
ultraviolet photolithography to pattern the S–D electrodes and interconnects
using an etch-back scheme with a commercial wet etchant (Transene, TFA) to
remove gold in exposed areas. After that we used oxygen reactive-ion etching
(200mtorr, 20s.c.c.m., O2flow, 100-W radio frequency power) to remove
SWNTs outside channel regions that were protected by a patterned layer of
photoresist (Shipley 1805).
This step can also be carried out on the plastic substrate after transfer, which
avoids the dimensional instability associatedwith polymer shrinkage during the
curing process and device failure due to incomplete transfer of the S–D electro-
des.However,itwillleadtoinferiordeviceperformance,owingtothesynergetic
effect of a smaller contact area between the S–D electrodes and the partially
embedded SWNTs, as well as a smaller effective channel width when we use
photolithographytodefineSWNTstripsasdescribedaboveonpolymersurfaces
thatarerelativelyrough(incomparisonwiththesurfaceroughnessofthesilicon
wafers; Supplementary Fig. 3). Therefore, this approach is only used in fabric-
atingrow-decodercircuits,whichprocesshasthehighestrequirementsondevice
yield.
Transfer-printing process. The transfer-printing process involved spin-casting
(1,500 r.p.m., 60s) polyamic acid (PAA, Aldrich) onto the SiO2–Si wafer with
SWNTs and S–D patterns, and then heating at 110uC for 3min to remove the
solvent. On the target polyimide (PI) substrate (DuPont, Kapton E; thickness
,50mm),wespin-cast(5,000r.p.m.,60s)afilmofpolyurethane(PU,NEA121).
Beforethisstep,wethermallycycledthePIbetween30uCand270uCtoimprove
its dimensional stability35. We laminated this PU-coated substrate on top of the
PAA–SiO2–Si wafer with the PU facing towards the PAA film, and applied
pressure on the back of the wafer to remove air bubbles. Heating them together
to 135uC for 30min thermally cured the PU film, thereby binding the PI sub-
stratetothePAAfilm.PeelingoffthePIsubstrateliftedthefilmofPU–PAAwith
embedded SWNT networks and S–D electrodes off the SiO2–Si wafer, with one
sideoftheS–Delectrodesexposed.Inthefinalstepavacuumoven(basepressure
of 300mtorr) with nitrogen flow (500s.c.c.m.) was used to thermally cure the
PAA to the PI through imidization reaction36.
Gate dielectric deposition. The gate dielectric was deposited on top of the PAA
after the latter had been cured to the PI. In the first step, 30nm of HfO2was
deposited by electron-beam evaporation (Temescal BJD 1800; base pressure of
231026torr) at a relatively low deposition rate (,0.5A˚s21) as measured by a
quartz crystal thickness monitor. This layer served as a protective layer for
SWNTs against highly reactive precursors used in a subsequent atomic layer-
deposition (ALD) process37. After evaporation, the sample was transferred
immediately to the ALD chamber to preserve the hydrophilicity of the freshly
deposited HfO2, which facilitates the growth of high-quality, pin-hole-free ALD
film. The ALD HfO2film (12nm) was deposited using a commercial ALD
reactor (Cambridge Nanotech, Savannah 100). One ALD reaction cycle consists
of one dose of water followed by a 5-s exposure and a 300-s purge, and then one
dose of Hf(NMe2)4followed by another 5-s exposure and a 270-s purge. During
deposition, the nitrogen flow was fixed at 20s.c.c.m. and the chamber temper-
ature was set at 120uC. The low deposition temperature prevents cracking of
HfO2due to the mismatch of thermal expansion coefficients but requires very
long purging time to remove excess precursors absorbed on the surface, to
prevent chemical-vapour-deposition-type reactions in the chamber38.
Via opening and gate/interconnect pattering. After the dielectric had been
deposited, the gate pattern was defined in another photolithography step. A
lift-off scheme was used to allow alignment of gate electrodes to the S–D elec-
trodesusing previously patterned alignment markers.Metal for thegate electro-
des (120nm aluminium or 2nm chromium–120nm gold) was deposited by
electron-beamevaporation(TemescalBJD1800;basepressureof331026torr).
In this metallization step (as well as the next step, for defining interlayer inter-
connects) two angled evaporations (incidence angle, 60u) with substrates placed
at opposite orientations and a blanket evaporation (incidence angle, 90u) were
performed to ensure that the metal layers covered the underlying surface topo-
graphy, thereby avoiding open points that would otherwise form in the inter-
connect lines. In all cases, the deposition rate must be within 4–7A˚s21. If the
evaporation rate is lower than 4A˚s21, accumulated heat can lead to cracking of
thePUlayer;iftheevaporationrateishigherthan7A˚s21,thestrainaccumulated
in the metal film can lead to defect formation in the lift-off process.
Following deposition, the lift-off was accomplished by soaking in acetone for
10min, followed by a short ultrasonic treatment (30s) to ensure that the lift-off
processwascomplete.BecausetheSWNTswerecoveredbyHFO2,theultrasonic
treatment did not damage the nanotube network. (Prolonged acetone soaking
can dissolve, at a low rate, the PI cured from PAA, owing, presumably, to
incomplete imidization.) Contact pads for probing and vias for interlayer inter-
connects were exposed by photolithography using AZ 5214 photoresist. A hard
bake (120uC, 2min) of the photoresist was performed before hydrofluoric acid
etching (4s in concentrated HF solution) of HfO2(ref. 39) to improve the
adhesion between the photoresist and the HfO2. We note here that in this step
thegoldpadspatternedintheS–Dlayerunderviasmustbelargerinsizethanthe
via holes to protect the PU from being etched by the hydrofluoric acid through
acidolysis reaction. The interlayer interconnect (5nm chromium–100nm gold)
was patterned using a lift-off process and photolithography. The patterning of
gate electrodes and interconnects were carried out separately because (1) the
predefined gate layer can also serve to protect the gate dielectric against possible
defectsexistinginthephotoresistmasklayer,preventingthecreationofpinholes
inthechannelregioninthewetetchingstep,and(2)aluminiumtendstoform a
poor contact with the gold S–D electrodes, possibly because of intermetallic
formation40, such that a different interconnect metal, such as the chromium–
goldcombination,wasnecessarywhenusingaluminiumgates.Finally,thecom-
pleted device/circuit was aged in air for 24h, and then thermally annealed at
120uC for 30min, to achieve stable operation.
Device and circuit characterizations. Direct-current measurements of SWNT
transistors and circuits were carried out in air using a semiconductor parameter
analyser (Agilent, 4155C), operated by Agilent Metrics I/CV Lite software (ver-
sion2.1) andGBIP communication. Triaxial andcoaxial shielding was incorpo-
rated into a Signatone probe station to achieve a better signal-to-noise ratio. A
precision LCR meter (Agilent, 4282A) was used for capacitance and impedance
measurements. Alternating-current input signals were generated by a function
generator (GW Instek, GFG-8219A). The output signals were measured using a
standard oscilloscope (Tektronix, TDS 3012B).
doi:10.1038/nature07110
©2008 Macmillan Publishers Limited. All rights reserved

Page 10

Stick percolation simulation. We constructed a sophisticated first-principles
numerical stick percolation model for the above random SWNT network by
generalizing the random network theory20,41,42. The model randomly populates
a two-dimensional grid with sticks of fixed length (LS) and random orientation
(h) and determines Ionthrough the network by solving the percolating electron
transport through individual sticks. In contrast to classical percolation, the
SWNT network is a heterogeneous network: one-third of the carbon nanotubes
are metallic and the remaining two-thirds are semiconducting. Because LCand
LShere are much larger than the phonon mean free path, linear-response trans-
portobviatestheneedtosolvethePoissonequationexplicitly.Thesystemiswell
described by drift–diffusion theory within individual stick segments of this ran-
dom stick network. The low-bias drift–diffusion equation, J5qmndQ/ds (where
J is current density, q is carrier charge, m is mobility, n is carrier density, Q is
electropotentialands islengthalongthetube),whencombinedwiththecurrent
continuity equation, dJ/ds50, gives the non-dimensional potential Qialong
tube i as:
d2Q
ds2{Cij(Qi{Qj)~0
HereCij5G0/G1isthedimensionlesscharge-transfercoefficientbetweentubesi
and j at their intersection point. G0<0.1e2/h and G15qnm/Dx are the mutual-
andself-conductancesofthetubes,respectively,andeistheelementarycharge,h
is Planck’s constant and Dx is the grid spacing. The density of the random stick
network is measured in area normalized by LS, and the density of our SWNT
network was ,40 according to scanning electron microscope measurements.
The finite-length strips were simulated by imposing a reflecting boundary con-
dition at the edge of each strip.
SPICE simulation. We described the behaviour of the SWNT thin-film transis-
tors as that of a PMOS field-effect transistor parallelly connected with an expo-
nential current source dependent on voltage (VGSand VDS). The PMOS field-
effect transistor was modelled using a standard square-law model with channel-
length modulation and S–D resistance effects. The exponential current source
wasusedtomimictheambipolarcurrent(Iambipolar),whichledtoanexponential
increase in Ioffwith increasing VDS. We expressed the exponential term in the
form of a Taylor series
Iambipolar~Kn(VGSzVG0) 1zVxzV2
x
2z???
??
where
Vx5VThreshold1aVGS2bVDS, and thefirst three terms wereincorporatedinto
the SPICE model. All fitting parameters were extracted from measured I–V
characteristics (summarized in Supplementary Table 1). The channel-length
scaling behaviour of these SWNT random network transistors can only be
Kn
andVG0
arefittingparametersandVx
isdefinedas
capturedbyourpercolationmodelling.Theresultsofsuchmodels(forexample,
off-stateresistances)canbeusedasinputstotheSPICEmodelstocapturethefull
range of behaviours.
The above model was then used in designing and simulating digital logic
circuits43. In transientsimulation,loadcapacitancewascalculatedautomatically
from measured overlap capacitance (330nFcm22) and gate capacitance
(80nFcm22) per unit area as well as estimated contact resistance (11kV), by
the HSPICE program. Although the measured voltage responses of fabricated
circuits agreed well with the design specifications, the current load responses
showed behaviour only qualitatively similar to the simulation results
(Supplementary Fig. 9). This deviation may be due to the relatively large
batch-to-batch variations in device performance, which influenced the current
load more significantly than they did the voltage responses.
31. Plummer, J. D., Deal, M. D. & Griffin, P. B. Silicon VLSI Technology: Fundamentals,
Practice and Modeling Ch.4 (Prentice Hall, Upper Saddle River, New Jersey,
2002).
32. Li, Y. M. et al. Growth of single-walled carbon nanotubes from discrete catalytic
nanoparticles of various sizes. J. Phys. Chem. B 105, 11424–11431 (2001).
33. Maria, J., Malyarchuk, V., White, J. & Rogers, J. A. Experimental and
computationalstudiesofphaseshiftlithographywithbinaryelastomericmasks.J.
Vac. Sci. Technol. B 24, 828–835 (2006).
34. Menard, E.etal.Micro-andnanopatterning techniquesfororganic electronic and
optoelectronic systems. Chem. Rev. 107, 1117–1160 (2007).
35. Zhou, L. S., Jung, S. Y., Brandon, E. & Jackson, T. N. Flexible substrate micro-
crystalline silicon and gated amorphous silicon strain sensors. IEEE Trans. Electron
Devices 53, 380–385 (2006).
36. Brekner, M. J. & Feger, C. Curing studies of a polyimide precursor. 2. Polyamic
acid. J. Polym. Sci. Pol. Chem. 25, 2479–2491 (1987).
37. Javey, A. et al. High-kappa dielectrics for advanced carbon-nanotube transistors
and logic gates. Nature Mater. 1, 241–246 (2002).
38. Hausmann, D. M., Kim, E., Becker, J. & Gordon, R. G. Atomic layer deposition of
hafnium and zirconium oxides using metal amide precursors. Chem. Mater. 14,
4350–4358 (2002).
39. Fujii, S., Miyata, N., Migita, S., Horikawa, T. & Toriumi, A. Nanometer-scale
crystallization ofthin HfO2 filmsstudied byHF-chemicaletching. Appl. Phys.Lett.
86, 212907 (2005).
40. Philofsk,E.Intermetallicformationingold-aluminumsystems.SolidStateElectron.
13, 1391–1399 (1970).
41. Kumar, S., Murthy, J. Y. & Alam, M. A. Percolating conduction in finite nanotube
networks. Phys. Rev. Lett. 95, 066802 (2005).
42. Pimparkar, N. et al. Current-voltage characteristics of long-channel nanobundle
thin-film transistors: A ‘‘bottom-up’’ perspective. IEEE Electron Device Lett. 28,
157–160 (2007).
43. Rabaey, J. M. Digital Integrated Circuits: A Design Perspective (Prentice Hall, Upper
Saddle River, New Jersey, 2002).
doi:10.1038/nature07110
©2008 Macmillan Publishers Limited. All rights reserved