Recent Advances in High Density Area Array Interconnect Bonding for 3D Integration
ABSTRACT The demand for more complex and multifunctional micro systems with enhanced performance characteristics for military applications is driving the electronics industry toward the use of best-of-breed materials and device technologies. Threedimensional (3-D) integration provides a way to build complex microsystems through bonding and interconnection of individually optimized device layers without compromising system performance and fabrication yield. Bonding of device layers can be achieved through polymer bonding or metal-metal interconnect bonding with a number of metalmetal systems. RTI has been investigating and characterizing Cu-Cu and CulSn-Cu processes for high density area array imaging applications, demonstrating high yield bonding between sub-I5 11m pads on large area array configurations. This paper will review recent advances in the development of high yield, large area array metal-metal interconnects which enable 3-D integration of heterogeneous materials (e.g. HgCdTe with silicon) and heterogeneous fabrication processes (e.g. infrared emitters or microbolometers with ICs) for imaging and scene projector applications.
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ABSTRACT: Non-collapsible Cu-Sn bumps (Cu pillars capped with a thin layer of Sn) have been studied recently as a means to vertically interconnect device layers, achieving 3D integrated circuits. The use of Cu-Sn bump structures is attractive for 3D integration for two primary reasons: 1) the rigid nature of the Cu bump allows for very fine pitch interconnections to be made with less risk of bridging than would exist with collapsible solder bumps, and 2) the joint created when bonding Cu and Cu-Sn bumps remelts at a higher temperature than the formation temperature, which allows for the stacking of multiple layers of devices without disturbing the interconnections achieved in previous bonding events. In order to understand the optimal structure and bonding process for fine pitch Cu-Sn bumps, a study was done to investigate the effects of Sn thickness and bonding pressure on the thickness and chemical composition of the bondline between Cu and Cu-Sn bumps. The thermal stability of the bondline was studied by subjecting bonded test samples to multiple temperature/pressure cycles. The bonding strength was evaluated through die shear tests, and the results were correlated with the parameters of the bump structure and with process parameters.Electronic Components and Technology Conference, 2007. ECTC '07. Proceedings. 57th; 07/2007
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ABSTRACT: Using standard single damascene type techniques on bulk-Si, combined on one hand with extreme wafer thinning and on the other with Cu-Cu thermo-compression bonding technology, the paper demonstrate yielding 10k through-wafer 3D-via chains with a via pitch of 10μm for a via diameter of 5μm. The bonded contacts exhibit shear strengths exceeding 40MPa. Measurements indicate there is no significant contact resistance at the Cu-Cu bonded interface: within measurement accuracy, the 4-point via chain resistance is consistent with bulk Cu resistivityElectron Devices Meeting, 2006. IEDM '06. International; 01/2007
Boise State University
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Recent Advances in High Density Area Array
Interconnect Bonding for 3D Integration
J. M. Lannon, J.
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paper are prohibited. DOI:10.1117/12.850305
J. M. Lannon, J.; C. Gregory; M. Lueck; A. Huffman; D. Temple; Amy J. Moll; and William B. Knowlton
This conference proceeding is available at ScholarWorks:http://scholarworks.boisestate.edu/mse_facpubs/8
Recent Advances in High Density Area Array Interconnect Bonding
for 3-D Integration
J. M. Lannon Jr.l*, C. Gregoryl, M. Lueck1, A Huffman1, D. Temple1, AJ. Mo112, and W.B.
1 RTI International, Research Triangle Park, NC;
2 Boise State University, Boise, ID
The demand for more complex and multifunctional micro systems with enhanced performance characteristics for military
applications is driving the electronics industry toward the use of best-of-breed materials and device technologies. Three-
dimensional (3-D) integration provides a way to build complex microsystems through bonding and interconnection of
individually optimized device layers without compromising system performance and fabrication yield. Bonding of
device layers can be achieved through polymer bonding or metal-metal interconnect bonding with a number of metal-
metal systems. RTI has been investigating and characterizing Cu-Cu and CulSn-Cu processes for high density area array
imaging applications, demonstrating high yield bonding between sub-I5 11m pads on large area array configurations.
This paper will review recent advances in the development of high yield, large area array metal-metal interconnects
which enable 3-D integration of heterogeneous materials (e.g. HgCdTe with silicon) and heterogeneous fabrication
processes (e.g. infrared emitters or microbolometers with ICs) for imaging and scene projector applications.
Keywords: 3-D integration, IC stacking, high density area arrays, IR emitters, microbolometers, IR detector arrays.
3-D integration technologies provide a technology path for miniaturization of systems/platforms, decreasing device weight
and power requirements, and increasing data rates between chips for a wide range of military and commercial applications
. These technologies enable opportunities for integrating (stacking) dissimilar materials and device technologies into
smaller, lighter, lower power, and higher signal processing packages for a variety of applications, including infrared (IR)
imaging and scene projector applications. For example, 3-D integration can remove the real-estate limitations of
hybridizing IR detector arrays to Si read-out ICs (ROICs) by allowing multiple layers of ICs with different functionalities
(e.g., analog and digital ICs) to be stacked with short interconnect paths and large inter-layer signal bandwidth through
bonding and interconnection of device layers. Further, the performance of a 3-D integrated detector array would be greatly
enhanced through on-chip decision making . The ability to separate different functionalities of Si circuitry into different
device layers is significant because it allows ICs based on different processes and design rules to be fabricated as separate
components (instead of monolithically). As a result, fabrication processes for the specific functionalities (e.g., sensing,
emitting, or signal driving/processing) can be optimized to increase yield and reduce costs without many of the thermal
budget, device real estate, and processing limitations inherent in monolithic approaches.
Of the bonding techniques available for creating 3D integrated devices, metal-metal bonding is the most compatible with
die-to-die and die-to-wafer configurations for facilitating processing of known-good-die (the preferred route for
integrating chips from low-yielding IC processes) and integrating chips of heterogeneous materials [3, 4].
Thermocompression bonding between arrays of Cu pads (Cu-Cu bonding) and solid-liquid diffusion bonding between
arrays of Cu and CuiSn pads (CulSn-Cu bonding) have been investigated for vertical integration of two or more devices.
The rigid nature of these non-collapsible pad structures allows for very fine pitch interconnections to be made with low
risk of bridging between neighboring interconnects. In addition, the metal-metal bonds are mechanically stable during
subsequent thermal processes, which allows for the stacking of multiple layers of devices without disturbing the
interconnections formed in previous bonding cycles.
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Technologies for Synthetic Environments: Hardware-in-the-Loop Testing XV,
edited by James A. Buford, Jr., Robert Lee Murrer, Jr., Proc. of SPIE Vol. 7663, 766305
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Proc. of SPIE Vol. 7663 766305-1
The choice of the bonding metallurgy is primarily dictated by the device surface topography and the thermal budget of
the devices. Previous work showed that the bonding yield of rigid bump structures is critically dependent on a number
of factors, including the intrinsic flatness of the device, the degree of planarity with which the devices can be aligned to
one another, and the interconnect pad height uniformity . The use of CuiSn pads provides some compliance for the
bonding process, compensating for small height variations arising from these factors while maintaining high bonding
yields. The compliance afforded by the CulSn-Cu bonding system is due to the wetting action of the Sn on the opposing
Cu pad when the Sn is heated above its melting temperature (232°C), leading to bond formation through solid-liquid
diffusion [4, 5]. Since the CulSn-Cu bonding process can be executed at temperatures below 300°C, CulSn-Cu bonding
consumes less of the thermal budget of ICs and subjects the bonded structures to lower thermal stresses than Cu-Cu
thermocompression bonding. Cu-Cu bonding has been investigated because the Cu-Cu bond contains no intermetallic
phases and therefore the joining interface is theoretically mechanically stronger than the CU6SnS and CU3Sn intermetallic
phases formed in CulSn-Cu bonding. Cu-Cu bonding may also be preferred for ICs with Cu top metal structures
because less back-end-of-line (BEOL) processing is required for the Cu terminated ICs.
Control of the device surface topography is important to achieve a high yielding bonding process for both metal-metal
bonding systems. Ideally, devices would be fabricated with the final inorganic passivation layer (typically Si3N4 and/or
Si02) planarized by a chemical-mechanical polish (CMF) process, thus providing a flat surface on which to fabricate the
metal interconnect pads. This is not always the case, however, and it is common for devices to have surface
topographies that vary by 1-2 microns, which is enough to significantly impact the bonding yield. Therefore, a flexible
process that provides a flat surface for formation of the metal interconnect pads and a process that can be extended to
most devices is required.
The feasibility of vertically stacking die by Cu-Cu interconnect bonding performed at 300°C and by CulSn-Cu bonding
of small arrays at temperatures < 300°C has been demonstrated by various groups [6. 7]. In this paper, we report on the
fabrication and bonding of large area array test devices with high yield Cu-Cu and CulSn-Cu bonding processes for
interconnect pads :s 15 11m in diameter. Bonding was performed without the use of resins or fixing agents. The bond
strengths and bond yield, as derived from die shear force measurements, post die shear inspections and electrical
measurements, are presented. Cross sections of bonded samples were analyzed to investigate the bond-line formation
between interconnect structures. Isothermal aging experiments were also performed to determine the long term stability
of the bond interfaces; the aged samples were characterized through electrical measurements and/or die shear testing.
Fabrication and bonding techniques for uniform area array bonding and scaling up to higher density arrays are also
The area array test vehicle used in these experiments was built on a 200 mm wafer with two different daisy chain
patterns. The pad layout was based on a pixilated readout IC designed by Fermi National Accelerator Laboratory for use
in high energy physics detector applications. While the minimum I/O pitch on the device was 50 11m, the interconnect
pad structures were designed to ultimately be compatible with 20 11m 110 pitch. In addition, while the original I/O layout
was a sparsely populated area array, interconnect pads were added to the test vehicle to create a full area array pattern
with uniform 50 11m pitch in the horizontal and vertical directions. The full array was 176 x 128 (22,528 total bumps)
with a chip size approximately 8mm x 8 mm. Details regarding test chip fabrication were previously reported .
It is important to note that two patterns ('device array' and 'full array') were designed to form daisy chain structures for
electrically probing assemblies after bonding. As seen in Figure 1, the device array layout connects every 8th pair of
adjacent bumps in a row (channel) to create a daisy chain of 22 interconnects. This pattern replicated the electrical
connections that would exist on the functional CMOS device with the non-daisy-chained pads serving as mechanical
(electrically passive) support structures only. The full array layout connects all 176 interconnect pads in each row. The
Si02 passivated daisy chains on the device array produced topographical differences between the daisy-chained and
non-daisy-chained pads. Prior to the formation of the final pads, the oxide layer was planarized by a chemical-
mechanical polish (CMF). Two different plating templates were also designed to provide interconnect pads of different
sizes. One plating template formed pads with 7 11m base diameters over the entire test vehicle; the other template
ProC. of SPIE Vol. 7663 766305-2
Fig. l. Optical micrographs of full and device array daisy chain test structure layouts.
contained die with pad arrays of either 11 or 15 11m base diameters.
misalignment tolerance for the bonding of 7 11m pad arrays to the larger pad arrays.
The larger diameter pads provide some
Once the interconnect pad fabrication process was completed, wafers were diced to singulate the test devices and parts
were bonded via thermocompression bonding with the parts held together under heat and pressure in order to form the
metal-metal bond. Sample bonding was performed in a Suss Microtech FC150 precision bonder with nitrogen purge.
Prior to bonding, the CuiSn pad chips were treated with the Plasma Assisted Dry Soldering process (PADS); a process
that converts the surface Sn oxides into a brittle oxy-fluoride compound which breaks up under pressure during the
bonding process, allowing the sub-surface Sn to flow to the surface and react with the contacted Cu surface . The Cu
pad chips were also chemically pre-treated with a weak sulfuric acid solution to remove Cu oxides immediately prior to
bonding. Preliminary experiments were performed for both metal-metal systems and the bonding conditions shown in
Table 1 were identified as good conditions for generating a high yielding sample set for comparison of the two systems.
The bonding pressures shown in Table 1 correspond to applied forces per interconnect of 1.33 g and 0.4 g for Cu-Cu and
CulSn-Cu interconnect bonding, respectively.
Table 1: Metal-Metal Bonding Conditions
The bonded samples were characterized by two-wire probing of electrical connectivity, die shear testing of mechanical
strength, and cross-section secondary electron microscopy (SEM).
instruments Model 550 bond test system containing a maximum 10 kg load cell die shear head; samples were held in a
fixture that clamped the bottom die while a shearing force was applied to the upper die. Visual inspections of the failure
interfaces were conducted on all die sheared samples to identify the failure modes and any bonds that did not form
during the bonding process. Thermal reliability of metal-metal bonded interconnects was determined from die shear
tests of isothermally aged samples. Isothermal aging was performed by storing samples for a period of time (500 or
1000 hours) in a SUN Systems oven held at 150aC in ambient atmosphere.
Die shear tests were performed on a Royce
Proc. of SPIE Vol. 7663 766305-3