Memory Models for an Application-Specific Instruction-set Processor Design Flow
Dept. of Inf. Eng. & Comput. Sci., Feng Chia Univ., Taichung
DOI: 10.1109/ICESS.2008.40 Conference: Embedded Software and Systems, 2008. ICESS '08. International Conference on
To optimize system performance for a specific target application, embedded system designers may add some new instructions, called application-specific instructions (ASIs), by automatic design flow. In past days, most application-specific instruction-set processor (ASIP) researches focus on reducing instruction latency to improve performance regardless of the impact of memory access. In this paper, a design flow is proposed to automatically generate ASIs and to compare the performance between considering register transferring and regardless of it. The experiment results show the proposed approach can achieve up to 14% performance improvement and 10% memory access reduction comparing to no register transferring consideration.
Data provided are for informational purposes only. Although carefully collected, accuracy cannot be guaranteed. The impact factor represents a rough estimation of the journal's impact factor and does not reflect the actual current impact factor. Publisher conditions are provided by RoMEO. Differing provisions from the publisher's actual policy or licence agreement may be applicable.