Band offset FinFET-based URAM (Unified-RAM) built on SiC for multi-functioning NVM and capacitorless 1T-DRAM

Abstract

A FinFET-based unified-RAM (URAM) using the band offset of Si/SiC is demonstrated for the fusion of a non-volatile memory (NVM) and capacitorless 1T-DRAM operation. An oxide/nitride/oxide (O/N/O) gate dielectric and a floating body caused by the band offset are combined in a bulk FinFET to allow two memory operations in a single transistor. The device is fabricated on an epitaxially grown Si/SiC substrate and its process is fully compatible with a conventional bulk FinFET SONOS. Highly reliable NVM and high speed 1T-DRAM operation are confirmed in a single URAM cell.

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Band Offset FinFET-Based URAM (Unified-RAM) Built on SiC
for Multi-Functioning NVM and Capacitorless 1T-DRAM

Jin-Woo Han1, Seong-Wan Ryu1, Sungho Kim1, Chung-Jin Kim1, Jae-Hyuk Ahn1, Sung-Jin Choi1, Kyu Jin Choi2, Byung Jin Cho1
Jin Soo Kim3, Kwang Hee Kim3, Gi Sung Lee3, Jae Sub Oh3, Myong Ho Song3, Yun Chang Park3, Jeoung Woo Kim3, and Yang-Kyu Choi1
1EECS, KAIST, Daejeon, Korea, 2Jusung Engineering, Gwangju, Korea, 3National Nanofab Center, Daejeon, Korea
E-mail: ykchoi@ee.kaist.ac.kr, Phone: +82-42-869-3477, Fax: +82-42-869-8565

Abstract
A FinFET-based unified-RAM (URAM) using the band offset of
Si/SiC is demonstrated for the fusion of a non-volatile memory (NVM)
and capacitorless 1T-DRAM operation. An oxide/nitride/oxide (O/N/O)
gate dielectric and a floating body caused by the band offset are
combined in a bulk FinFET to allow two memory operations in a single
transistor. The device is fabricated on an epitaxially grown Si/SiC
substrate and its process is fully compatible with a conventional bulk
FinFET SONOS. Highly reliable NVM and high speed 1T-DRAM
operation are confirmed in a single URAM cell.
Introduction
In the digital convergence era, the development of multi-functional or
fusion memory holds particular attraction [1-3]. An example of fusion
memory, NVM and 1T-DRAM can be operated in a single memory cell,
and these operations are identified by the bias conditions of Vg and Vd
as shown in Fig. 1. We recently proposed a FinFET SONOS URAM
fabricated on a SOI substrate [3]. However, the SOI substrate is prone
to heat dissipation, which degrades the sensing window for 1T-DRAM
[4]. In the present work, we propose a band offset URAM architecture
built on Si/SiC for effective management of heat and reduced
fabrication cost.
A buried n-well layer that serves as a barrier to hold holes has been
employed in a bulk substrate for 1T-DRAM whereas a buried oxide has
been used in SOI [5-6]. However, with the deep implantation process
for the buried n-well, it is difficult to accurately define the abrupt
doping profile. Thus, epitaxially grown Si/SiC to hold holes by the band
offset is proposed. A FinFET-based URAM is also fabricated on a
buried n-well as a control group.
Device Fabrication
The process sequence is summarized in Fig. 2. First, a Si/Si0.99C0.01
layer is epitaxially grown for the band offset, and buried n-implantation
is carried out in the case of the control group. The subsequent steps
correspond with those of the bulk FinFET SONOS process flow [7].
The fabricated device dimensions and parameters are summarized in
Table 1. SEM/TEM images are shown in Fig. 3. Si/SiC lattices are
perfectly matched as shown in the fast Fourier transformed images. The
SIMS profile for the buried n-well device is shown in Fig. 4.
Results and Discussion
NVM characteristics - Fig. 5 shows the speed response of P/E carried
out by a FN-tunneling mechanism. Both devices show similar threshold
voltage (VT) shift. Fig. 6 shows the reliability characteristics. 10 year
retention behaviors are observed along with a more than 3V VT
window; however, the Si/SiC device shows better data retention time. In
addition, excellent endurances of more than 107 P/E cycles are observed
without VT window degradation for both devices.
1T-DRAM characteristics – A floating body effect in bulk devices is
originated from the buried n-well or the valence band offset of Si/SiC. Fig.
7 shows the 1T-DRAM operation mechanism. For programming, the holes
generated by impact ionization are stored in the Si body on band offset.
For erasing, accumulated holes are eliminated by the forward biased drain.
As evidence of holes accumulation, a kink appears in the ID-VD curves, as
shown in Fig. 8. A simulated contour of the hole concentration in Fig. 9
clearly shows that both the buried n-well and the band offset of Si/SiC can
store holes. Fig. 10 shows the P/E characteristics for the 1T-DRAM
operation.
Fig. 11 shows the P/E speed response. The Si/SiC device exhibits a
wider sensing window than the buried n-well device. At
τPGM=τERS=20nsec, the sensing window in Si/SiC (ΔIS=10μA) allows a
retention time of 50msec whereas the buried n-well (ΔIS=6μA) retains
data during 10msec. If the retention time is increased, faster operation
can be possible because of the saved refresh time. One important
advantage in bulk devices is a tunable substrate voltage. By modulation
of the substrate voltage, the barrier height to hold holes can be adjusted.
As shown in Fig. 12, positive VSUB (0.1V<VSUB<0.3V) raises the barrier
height resulting in increment of the retention time. In contrast,
VSUB>0.4V reduces the retention time due to a forwardly biased
substrate-drain junction. Although doubled retention time was observed
in the buried n-well device by optimal VSUB, Si/SiC still shows superior
performance to the buried n-well device. Furthermore, these
characteristics the Si/SiC device can be improved by increment of the
content of C in SiC, as this will provide an enlarged valence band offset
[8]. Impact ionization for 1T-DRAM programming can adversely
stimulate charges to be trapped in the O/N/O layer, and consequently an
undesired soft program can be possible in NVM. In order to examine
interference between these two operations, ID-VG characteristics are
compared before/after 1T-DRAM operation. As shown in Fig. 13,
interference by the impact ionization is found to be negligible.
Conclusions
A band offset FinFET-based unified-RAM (URAM) on Si/SiC
substrate is demonstrated. URAM performs NVM and 1T-DRAM
functions in a single transistor with benefits of low cost and high heat
dissipation. NVM uses an O/N/O layer for charge trapping, and
1T-DRAM utilizes a floating body effect for capacitorless DRAM
operation in the bulk substrate.
References
[1] C. W. Oh et al., VLSI, p.58, 2006. [2] C. W. Oh et al., VLSI, p.168,
2007. [3] J.-W. Han et al., IEDM, p.929, 2007. [4] P. C. Fazan, et al.,
SPIE, p.489, 2002. [5] R. Ranica et al., VLSI, p.38, 2005. [6] R. Ranica
et al., VLSI, p.128, 2004. [7] J. R. Hwang. et al., IEDM, p.154, 2005. [8]
H. J. Osten et al., JAP, p. 2716, 1998.
978-1-4244-1805-3/08/$25.00 © 2008 IEEE2008 Symposium on VLSI Technology Digest of Technical Papers 200

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buried n-well
Si/SiC
Data ‘1’ Data ‘1’Data ‘0’Data ‘0’
buried n-well
Si/SiC
gate
oxide
SiC
p-
p-
n-
n-
gate
oxide
gate
oxide
impact ionization
forward biased current
p-
n-
gate
oxide
+
excess
hole
gate
oxide
SiCSiC
gate
oxide
++
excess
hole hole
excess
Erase
Forward
biased current
VG
Program
Impact
ionization
VG
Read Read
11VG
VD
VD
0.4 0.4
-1-1VD
VD
11VG
22VD
VD
11VG
Erase
Forward
biased current
Program
Impact
ionization
VG
Si substrateSi substrate
Hole barrier layerHole barrier layer
SiSi
SiO2
SiO2
SiO2
Hole barrier layer
Si substrate Si substrate
finfin
SiO2
Hole barrier layer
SiO2
SiO2
SiO2
Hole barrier layer
Si substrate
Fig. 2 : Process flow for bulk FinFET SONOS. An epitaxially grown Si/SiC
layer or a buried n-well is used for the hole barrier.
Si substrate
GateGate
fin fin
SiO2
Hole barrier layer
SiO2
SiO2
SiO2
Hole barrier layer
Si substrate Si substrate
Gate Gate
finfin
SiO2
Hole barrier layer
(1) (2)
(3) (4)
SiO2
SiO2
Hole barrier layer
Si substrate
Gate
fin
Gate
e e ee e eeee
Si substrate
eee eeeeee
Non-Volatile Memory (Flash)
Si substrate
Hole barrier layer
SD
h h h
Gate
High-Speed Memory (1T-DRAM)
|VG| (V)
|VD| (V)
Read
Impact
ionization
Hot-carrier
injection
e
eh
h
FN
tunneling
Gate Gate
SS
DD
S O N O
Fig. 3 : SEM/TEM images of the fabricated structure. Epitaxially grown Si/Si0.99C0.01films show perfect crystallinity.
5 nm5 nm5 nm5 nm
Gate
50 nm50 nm
50nm
S
Fin
Buried n wellBuried n well
50 nm50 nm50 nm50 nm
Si
SiC
Si
S iC
S i
S iC
1 1
2 2
1 1
2 2
p-type substrate
Fig. 1 : Schematics of URAM operation.
Table 1 : Fabricated device dimensions
and parameters of the measured device.
Fig. 5 : (a) Program and (b) erase speed characteristics for NVM operation. A
FN tunneling mechanism is used for both program and erase.
Fig. 6 : (a) Retention and (b) endurance characteristics for NVM operation. The
Si/SiC device shows better retention characteristics. Both devices exhibit excellent
endurance.
Fig. 9 : Hole concentration at impact
ionization condition in Fig. 7.
Fig. 10 : Program and erase characteristics
for 1T-DRAM operation. Si/SiC shows a
wider sensing window than buried n-well.
Fig. 13 : ID-VG curves before (lines) and
after (symbols) 1T-DRAM programming.
Fig. 8 : ID-VDcharacteristics. Kink
ensures a floating body effect.
Fig. 11 : P/E speed for 1T-DRAM. (a) Data ‘1’ state degradation is more severe
than data ‘0’ state. (b) Retention characteristics for 1T-DRAM. Si/SiC shows
wider sensing window and longer data retention.
Fig. 12 : Retention time as a function of
VSUB. 0.1<VSUB<0.3
condition.
is optimal
Fig. 4 : SIMS profile obtained on S/D
to substrate region in buried n-well
device.
Fig. 7 : Schematic diagrams for P/E of 1T-
DRAM and bias conditions used in this
work.

(a)
9595
115115
0.18 0.180.110.11
VT(V)VT(V)
110110
DIBL (mV/V)DIBL (mV/V)
9393
SS (mV/dec)SS (mV/dec)
4/6/44/6/4
TO/N/O(nm)TO/N/O(nm)
5050
Hfin(nm)Hfin(nm)
5050
Wfin(nm)Wfin(nm)
230230
Lg (nm)Lg (nm)
Buried n-wellBuried n-well Si/SiCSi/SiCParameter Parameter
10
-7
10
-6
10
-5
10
-4
10
-3
10
-2
10
-1
10
0
0
1
2
3
4
5
6
τ τPGM=100μ μsec
VG,PGM=9V
VG,PGM=13V
Si/SiC
Buried n-well
Threshold voltage (V)
Program time (sec)


10
-7
10
-6
10
-5
10
-4
10
-3
10
-2
10
-1
10
0
-2
-1
0
1
2
3
4
τ τERS=10msec
VG,ERS=-12V
VG,ERS=-15V


Threshold voltage (V)
Erase time (sec)
Si/SiC
Buried n-well
10
010
110
210
Retention time (sec)
310
410
510
610
710
810
9
-2
-1
0
1
2
3
4
5
4.8V
Δ ΔV=3.5V
10 years
Si/SiC
Buried n-well
VG,PGM=13V, τ τPGM=100μ μsec
VG,ERS=-15V, τ τPGM=10msec

Threshold voltage (V)
10
0
10
1
10
2
10
P/E cycles (#)
3
10
4
10
5
10
6
10
7
10
8
-2
-1
0
1
2
3
4
5
5.4V
Δ ΔV=4.6V
VG,ERS=-15V, τ τPGM=10msec
VG,PGM=13V, τ τPGM=100μ μsec


Threshold voltage (V)
Si/SiC
Buried n-well
0.00.51.01.52.0
0
10
20
30
40
50
Kink
VSUB=0V
VG=0 ~ 2V
0.5V step
Si/SiC
Buried n-well

Drain current (μ μA)
Drain voltage (V)
0510
Time (msec)
152025
0
2
4
6
8
10
12
14
16
18
20
22
24
τ τPGM=τ τERS=20nsec
Buried n well
Si/SiC
Sensing current (μ μA)
10
-8
10
-7
10
-6
10
-5
-10
0
10
20
30
40
50
60
70
80
90
τ τPGM=τ τERS=20nsec
VSUB=0V

Retention time (msec)
P/E time (sec)
Si/SiC
Buried n-well
10
-8
10
-7
10
-6
10
-5
4
6
8
10
12
14
16
18
20
22
24
6μ μA
Δ ΔIS=10μ μA
τ τPGM=τ τERS=20nsec
Data '0'
Data '1'
VSUB=0V
Sensing current (μ μA)
P/E time (sec)
Si/SiC
Buried n-well
(a)(b)
(a)(b)
(b)
-0.2 -0.1 0.0 0.1 0.2 0.3 0.4 0.5 0.6
Substrate volgate (V)
-20
0
20
40
60
80
100
Retention time (msec)
PN junction
current
Optimal
range
Si/SiC
Buried n-well
Hole barrier
Hole barrier
-0.50.00.51.01.52.0
10
-10
10
-9
10
-8
10
-7
10
-6
10
-5
10
-4
Line : before
Symbol : after
Si/SiC
Buried n-well
VD=0.05V
VSUB=0V

Drain current (A/μ μm)
Gate voltage (V)
• (100) bulk wafer
• Si/SiC epitaxial growth
vs.
• buried n-well implantation
• channel implantation
• fin patterning
• STI formation
• O/N/O and poly-Si formation
• gate patterning
• S/D formation
Si substrate
Buried n well
Gate
D
p-body
beam
0200400600800
10
16
10
17
10
18
10
19
10
20
10
21
p
-(body)
n
-(buried n-well)
n
+(S/D)
Concentration (Atom/cm
3)
Depth from Si surface (nm)
Buried
n-w elln-w ell
Buriedp-type
substrate
Index of hole Conc entration (/c m3)
9.89.810.610.6
1013
11.311.3
12.112.112.812.8
13.613.614.414.4
109
S iCS iC
p-type
substratesubstrate
p-type
1015
1015
1010
1013
978-1-4244-1805-3/08/$25.00 © 2008 IEEE2008 Symposium on VLSI Technology Digest of Technical Papers201