Conference Paper

Low Cost Implementation of Motion Estimation System Based on Diagonal Match Criterion

DOI: 10.1109/CISP.2008.569 Conference: Image and Signal Processing, 2008. CISP '08. Congress on, Volume: 2
Source: IEEE Xplore

ABSTRACT To reduce the excessive amount of computation of traditional motion estimation (ME) algorithm, the diagonal match criterion (DMC) was proposed. DMC brings 75% reduction of computation Complexity and just 2.08% reduction of performance (PSNR) compare with traditional ME algorithm. What’s more important is that beside low, the performance reduction is very stable. And this makes DMC a valuable criterion. However, at the implementing side, DMC brings much irregularity of data flow. So the Lean snake registers array (LSRA) was proposed to conquer the irregularity. With this problem solved, the implementation makes a good use of the advancement of the algorithm, leading to high speed with very low cost of PEs and bandwidth. The implementation was designed when DMC was used in full-search strategy. The implementation supports real-time processing of 720×576 video with 25 fps at 80 MHz for a search range of [-7, +7] and macro block size of 8.

0 Followers
 · 
35 Views
  • Source
    [Show abstract] [Hide abstract]
    ABSTRACT: This paper presents a novel memory architecture for motion estimation processor design. By means of conditional selection strategy, data items which can be reused are stored in memory banks and arranged in a snake-like way. Both integer and half pixel motion vectors can be obtained by the proposed architecture and an array processor, where memory bandwidth can be minimized and hence I/O pin-count can be reduced a lot. The proposed architecture is then demonstrated by a test chip, whose hardware efficiency of processor elements is 100% when integer motion vector is demanded
    Circuits and Systems, 1995. ISCAS '95., 1995 IEEE International Symposium on; 06/1995
  • Source
    IEEE Transactions on Circuits and Systems for Video Technology 01/1998; 8:124-127. DOI:10.1016/S0920-5489(99)90940-6 · 2.26 Impact Factor
  • [Show abstract] [Hide abstract]
    ABSTRACT: A description is given of VLSI architectures for block-matching algorithms utilizing systolic array processors. A well-known mapping procedure has been applied to derive the array processors from the algorithm. Examples of two- and one-dimensional systolic arrays are presented. The transistor-count of the architectures using presently available CMOS technology and their maximum processable frame rates for real-time computation of video signals have been estimated
    IEEE Transactions on Circuits and Systems 11/1989; 36(10-36):1301 - 1308. DOI:10.1109/31.44346