Conference Proceeding

VLSI decoding architecture with improved convergence speed and reduced decoding latency for irregular LDPC codes in WiMAX

Dept. of Electr. Eng., Nat. Tsing Hua Univ., Hsinchu
06/2008; DOI:10.1109/ISCAS.2008.4541469 ISBN: 978-1-4244-1683-7 pp.520 - 523 In proceeding of: Circuits and Systems, 2008. ISCAS 2008. IEEE International Symposium on
Source: IEEE Xplore

ABSTRACT In this paper, we modify a previously proposed decoding algorithm and propose a VLSI architecture to decode the quasi-cyclic low-density parity-check (QC-LDPC) code C used in the IEEE 802.16e standard. The modified decoding algorithm sequentially decodes a plurality of block codes for which its code length is much smaller than that of C. The proposed decoder can achieve a faster speed of convergence, lower decoding latency, higher throughput, and lower number of memory access as compared to the decoders using conventional turbo decoding message passing (TDMP) based on similar hardware complexity.

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Keywords

conventional turbo decoding message
 
convergence
 
lower decoding latency
 
lower number
 
memory access
 
modified decoding algorithm sequentially decodes
 
plurality
 
proposed decoding algorithm
 
quasi-cyclic low-density parity-check
 
similar hardware complexity
 
TDMP
 
VLSI architecture
 

Yeong-Luh Ueng