Conference Paper

Effects of Through-BOX Vias on SOI MOSFETs

Lincoln Lab., Massachusetts Inst. of Technol., Lexington, MA
DOI: 10.1109/VTSA.2008.4530815 Conference: VLSI Technology, Systems and Applications, 2008. VLSI-TSA 2008. International Symposium on
Source: IEEE Xplore

ABSTRACT The metal-filled vias through the buried oxide are integrated with silicon-on-insulator (SOI) MOSFETs. The FET temperature, measured directly using integrated junction diodes, can be lowered by as much as 25degC with these vias. In addition to enhanced DC characteristics, lowered gate resistance and output conductance further improve the RF performance and the extent of improvement is dependent on the FET design.

0 Bookmarks
 · 
52 Views
  • [Show abstract] [Hide abstract]
    ABSTRACT: 3D integration consists of 3D IC packaging, 3D IC integration, and 3D Si integration. They are different and in general the TSV (through-silicon via) separates 3D IC packaging from 3D IC integration and 3D Si integration since the latter two use TSV but 3D IC packaging does not. TSV (with a new concept that every chip or interposer could have two surfaces with circuits) is the heart of 3D Si integration and 3D IC integration and is the focus of this investigation. The origin of 3D Si integration and 3D IC integration is presented. Furthermore, the evolution and outlook of 3D Si integration and 3D IC integration are discussed as well as their road maps are presented. Finally, a generic, low-cost and thermal-enhanced 3D IC integration system-in-package (SiP) is proposed for high performance applications.
    Electronics Packaging Technology Conference (EPTC), 2010 12th; 01/2011
  • [Show abstract] [Hide abstract]
    ABSTRACT: 3D integration consists of 3D IC packaging, 3D IC integration, and 3D Si integration. They are different and in general, the TSV (through-silicon-via) separates the 3D IC packaging and 3D IC/Si integrations, i.e., the latter two use TSV, but 3D IC packaging does not. TSV for 3D integration is >26 years old technology, which (with a new concept that every chip could have two active surfaces) is the focus of this study. Emphasis is placed on the TSV manufacturing yield and hidden costs. A 3D integration roadmap is also provided.
    Electronic Components and Technology Conference (ECTC), 2010 Proceedings 60th; 07/2010
  • [Show abstract] [Hide abstract]
    ABSTRACT: 3D integration consists of 3D IC packaging, 3D IC integration, and 3D Si integration. They are different and in general the TSV (through-silicon via) separates 3D IC packaging from 3D IC/Si integrations since the latter two use TSV but 3D IC packaging does not. TSV (with a new concept that every chip or interposer could have two surfaces with circuits) is the heart of 3D IC/Si integrations and is the focus of this investigation. The origin of 3D integration is presented. Also, the evolution, challenges, and outlook of 3D IC/Si integrations are discussed as well as their road maps are presented. Finally, a few generic, low-cost, and thermal-enhanced 3D IC integration system-in-packages (SiPs) with various passive TSV interposers are proposed.
    Advanced Packaging Materials (APM), 2011 International Symposium on; 01/2011