Conference Paper

Adding Slow-Silent Virtual Channels for Low-Power On-Chip Networks

Keio Univ., Yokohama
DOI: 10.1109/NOCS.2008.4492722 Conference: Networks-on-Chip, 2008. NoCS 2008. Second ACM/IEEE International Symposium on
Source: DBLP


In this paper, we introduce the use of slow-silent virtual channels to reduce the switching power of on-chip networks while keeping the leakage power small. Adding virtual channels to a network improves the throughput until each link bandwidth is saturated. This enables us to reduce the switching power of on-chip networks by decreasing their operating frequency and supply voltage. However, adding virtual channels increases the leakage power of routers as well as the area due to their large buffers; so the runtime power gating is applied to individual virtual channels to eliminate this problem. We evaluate the performance of slow-silent virtual channels by using real application traces, and their power consumption (switching and leakage) is evaluated based on the detailed design of a virtual-channel router placed and routed with a 90 nm technology. These evaluation results show that a network with three or four virtual channels achieves the best energy efficiency in a uniform traffic. In the cases of neighboring communications, a network with two virtual channels is better than the other networks with more virtual channels, because the performance improvement from no virtual channel to two virtual channels is the largest and their frequency and supply voltage can also be reduced well in these cases.

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    • "In [19] powering down links is proposed. In [7] static power consumption is reduced by using the concept of on/off links [19] with power-aware buffers [4], [14], [15]. The proposed power management algorithm in this paper uses also the concept of on/off links. "
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    ABSTRACT: We present a novel network on-chip topology, PC-Mesh (Parallel Concentrated Mesh), suitable for tiled CMP systems. The topology is built using four concentrated mesh (C-Mesh) networks and a new network interface able to inject packets through different networks. The goal of the new combined topology is to minimize the power consumption of the network when running applications exhibiting low traffic rates and maximize throughput when applications require high traffic rates. Thus, the topology is dynamically adjusted (switching on and off network components) with a proper injection algorithm, adapting itself to the network on-chip traffic requirements. The PC-Mesh network performs as a C-Mesh network (using one sub network) when the traffic is low obtaining large savings in power consumption. When the load network increases, new sub networks are opened and thus higher traffic rates are supported, thus providing comparable results as the mesh network. Additional benefits of the PC-Mesh network is its fault tolerance degree and the lower latency in terms of hops. An alternative PC-Mesh version is provided to optimize the fault-tolerance degree. Comparative results with detailed evaluations (in area, power, and delay) are provided both for the network interface and switches. Results demonstrate PC-Mesh is able to dynamically adapt to the current traffic situations. Experimental results with a system-level simulation platform (including the application being run and the operating system) are provided. Results show how the PC-Mesh network achieves the same results as the C-Mesh topology reducing execution time of applications by 20% as well as energy consumption by also 20%, when compared with the 2D-Mesh network topology. However, when challenged with higher traffic demands, PC-Mesh outperforms the C-Mesh network by achieving much lower execution time of applications and lower energy consumption. In some scenarios, execution time is reduced by a factor of 2 and power cons- - umption by 50%.
    International Conference on Parallel Processing, ICPP 2011, Taipei, Taiwan, September 13-16, 2011; 01/2011
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    • "In [21] powering down links is proposed. In [9] static power consumption is reduced by using the concept of on/off links [21] with power-aware buffers [5], [16], [17]. The proposed power management algorithm in this paper uses also the concept of on/off links. "
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    ABSTRACT: In this paper, we present a flexible network on-chip topology: NR-Mesh (Nearest neighboR Mesh). The topology gives an end node the choice to inject a message through different neighboring routers, thereby reducing hop count and saving latency. At the receiver side, a message may be delivered to the end node through different routers, thus reducing hop count further and increasing flexibility when routing messages. This flexibility allows for maximizing network components to be in switch off mode, thus enabling power aware routing algorithms. Additional benefits are reduced congestion/contention levels in the network, support for efficient broadcast operations, savings in power consumption, and partial fault-tolerance. Our second contribution is a power management technique for the adaptive routing. This technique turns router ports and their attached links on and off depending on traffic conditions. The power management technique is able to achieve significant power savings when there is low traffic in the network. We further compare the new topology with the 2D-Mesh, using either deterministic or adaptive routing. When compared with the 2D- Mesh using deterministic routing, executing real applications in a full system simulation platform, the NR-Mesh topology using adaptive routing is able to obtain significant savings, 7% of reduction in execution time and 75% in energy consumption at the network on average for a 16-Node CMP System. Similar numbers are achieved for a 32-Node CMP system. Index Terms—topology; injection; power consumption;
    14th Euromicro Conference on Digital System Design, Architectures, Methods and Tools, DSD 2011, August 31 - September 2, 2011, Oulu, Finland; 01/2011
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    • "In this paper we build on these techniques with a focus on static power consumption. Our approach combines the concept of on/off links [17] with power-aware buffers [3] [12] [13] and extends power-awareness to switches and arbiters. "
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    ABSTRACT: Chip multiprocessors (CMPs) have emerged as a primary vehicle for overcoming the limitations of uniprocessor scal-ing, with power constraints now representing a key factor of CMP design. Recent studies have shown that the on-chip in-terconnection network (NOC) can consume as much as 36% of overall chip power. To date, researchers have employed several techniques to reduce power consumption in the net-work, including the use of on/off links by means of power gating. However, many of these techniques target dynamic power, and those that consider static power focus exclu-sively on flit buffers. In this paper, we aim to reduce static power consumption through a comprehensive approach that targets buffers, switches, arbitration units, and links. We es-tablish an optimal power-down scheme which we use as an upper bound to evaluate several static policies on synthetic traffic patterns. We also evaluate dynamic utilization-aware power-down policies using traces from the PARSEC bench-mark suite. We show that both static and dynamic policies can greatly reduce static energy at low injection rates with only minimal increases in dynamic energy and latency.
    Proceedings of the 2nd International Workshop on Network on Chip Architectures (NoCArc '09), New York, NY; 12/2009
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