Comparison of output drivers for high-speed serial links
ABSTRACT A comparison between the performance of a current-mode differential signaling driver and a voltage mode driver for high-speed (HS) serial links is presented. Minimum power consumption, minimum area, minimum added jitter, and maximum immunity to power supply noise are the main figures of merit. Both drivers employ on-chip termination to eliminate reflections and pre-emphasis to reduce inter-symbol-interference (ISI) in order to enhance signal integrity and operating speed. They are implemented in 0.13 mum CMOS process using 1.2-V power supply. Both drivers support multiple output voltages and pre-emphasis ratios.
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ABSTRACT: A current-mode output driver that supports SERDES applications is implemented using 0.13 mum Bulk and PD SOI CMOS technologies. Schematic simulation results confirm the enhanced performance of PD SOI for very high-speed interfaces. The PD SOI current-mode driver shows a 3 times lower data dependent jitter than the bulk current-mode driver at the same 3.125 Gbps data rate of XAUI standard.SOI Conference, 2009 IEEE International; 11/2009
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ABSTRACT: A 2.4 Gbps output driver for DDR3 memory interface with programmable de-emphasis scheme is proposed. There are 15 de-emphasis levels that can be programmed to eliminate inter-symbol interference (ISI) problem at high operating speed. The proposed output driver is implemented using low-voltage 45 nm CMOS process. Due to the DDR3 memory operating voltage is 1.5 V, transistor stacking technique is applied in the output driver design to avoid transistor gateoxide reliability issues. The driver's transmit impedance can be programmed between 20 Ω to 40 Ω and receive impedance of 100 Ω. The output slew rate is controlled at 4-6 V/ns. There are two compensation blocks to calibrate the output impedance and output slew rate across process, voltage, and temperature (PVT) variations.Intelligent and Advanced Systems (ICIAS), 2012 4th International Conference on; 01/2012