A comparison between the performance of a current-mode differential signaling driver and a voltage mode driver for high-speed (HS) serial links is presented. Minimum power consumption, minimum area, minimum added jitter, and maximum immunity to power supply noise are the main figures of merit. Both drivers employ on-chip termination to eliminate reflections and pre-emphasis to reduce inter-symbol-interference (ISI) in order to enhance signal integrity and operating speed. They are implemented in 0.13 mum CMOS process using 1.2-V power supply. Both drivers support multiple output voltages and pre-emphasis ratios.
"A current-mode differential driver has been more popular than a voltage-mode differential driver in a highspeed serial link for its immunity to power supply noise and ease of impedance matching . For the same voltage swing, the power consumption of a current-mode driver, however, is larger than that of a voltage-mode driver and therefore a voltage-mode driver is drawing lots of interest especially for low-power serial link  . "
[Show abstract][Hide abstract] ABSTRACT: A 6-Gb/s differential voltage mode driver is presented whose output impedance and pre-emphasis level can be controlled independently. The voltage mode driver consists of five binary-weighted slices each of which has four sub-drivers. The output impedance is controlled by the number of enabled slices while the pre-emphasis level is determined by how many sub-drivers in the enabled slices are driven by post-cursor input. A prototype transmitter with a voltage-mode driver implemented in a 65-nm CMOS logic process consumes 34.8-mW from a 1.2-V power supply and its pre-emphasized output signal shows 165-mVpp,diff and 0.56-UI eye opening at the end of a cable with 10-dB loss at 3-GHz.
Journal of Semiconductor Technology and Science 10/2013; 13(5). DOI:10.5573/JSTS.2013.13.5.423 · 0.52 Impact Factor
"In this context, the use of SOI technology can greatly enhance the performance of the SERDES output driver due to the inherently reduced junction capacitance . The current-mode driver described in  is implemented in this work using 0.13 µm Bulk CMOS and Partially-Depleted (PD) SOI technologies provided by the same foundry. "
[Show abstract][Hide abstract] ABSTRACT: A current-mode output driver that supports SERDES applications is implemented using 0.13 mum Bulk and PD SOI CMOS technologies. Schematic simulation results confirm the enhanced performance of PD SOI for very high-speed interfaces. The PD SOI current-mode driver shows a 3 times lower data dependent jitter than the bulk current-mode driver at the same 3.125 Gbps data rate of XAUI standard.
[Show abstract][Hide abstract] ABSTRACT: A 2.4 Gbps output driver for DDR3 memory interface with programmable de-emphasis scheme is proposed. There are 15 de-emphasis levels that can be programmed to eliminate inter-symbol interference (ISI) problem at high operating speed. The proposed output driver is implemented using low-voltage 45 nm CMOS process. Due to the DDR3 memory operating voltage is 1.5 V, transistor stacking technique is applied in the output driver design to avoid transistor gateoxide reliability issues. The driver's transmit impedance can be programmed between 20 Ω to 40 Ω and receive impedance of 100 Ω. The output slew rate is controlled at 4-6 V/ns. There are two compensation blocks to calibrate the output impedance and output slew rate across process, voltage, and temperature (PVT) variations.
Intelligent and Advanced Systems (ICIAS), 2012 4th International Conference on; 01/2012
Data provided are for informational purposes only. Although carefully collected, accuracy cannot be guaranteed. The impact factor represents a rough estimation of the journal's impact factor and does not reflect the actual current impact factor. Publisher conditions are provided by RoMEO. Differing provisions from the publisher's actual policy or licence agreement may be applicable.