A Novel Test Generation Methodology for Adaptive Diagnosis
ABSTRACT This paper presents a automatic test pattern generation technique to improve the diagnostic resolution of a given test set. Each test pattern generated by existing techniques detects a large number of faults. Identifying the faulty candidate from a large set of possible fault candidates is extremely difficult and time consuming. A novel framework to adoptively generate additional patterns for diagnosing the faulty location is presented. The additional patterns prune a set of fault free candidates from the possible fault candidates. The proposed technique improves the diagnostic resolution where each new pattern detects only a small number of faults and each fault is detected by few patterns. The proposed method is applicable to any fault model and distinguishes a large number of faults with a small number of patterns. For simplicity we demonstrate the effectiveness of the approach on the path delay fault model.
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ABSTRACT: The first non-enumerative framework for diagnosing path delay faults using zero suppressed binary decision diagrams is introduced. We show that fault free path delay faults with a validated non-robust test may together with fault free robustly tested faults be used to eliminate faults from the set of suspected faults. All operations are implemented by an implicit diagnosis tool based on the zero suppressed binary decision diagram. The proposed method is space and time non-enumerative as opposed to existing methods which are space and time enumerative. Experimental results on the ISCAS'85 benchmarks show that the proposed technique is on an average least three times more efficient to improve the diagnostic resolution than existing techniques.03/2003;
Conference Proceeding: An adaptive path delay fault diagnosis methodology [logic IC testing][show abstract] [hide abstract]
ABSTRACT: A framework to adaptively perform delay fault diagnosis is introduced. We propose a methodology to perform diagnosis taking into account the effect of test vectors on the propagation delay along a path. An ATPG capable of generating test vectors that cannot be invalidated due to process variations in the submicron technology is used for diagnosis purposes. The proposed framework also has the ability to generate tests that can take care of delay faults induced by noise. Experimental results on the ISCAS'85 benchmarks shows the effectiveness of the proposed technique.Quality Electronic Design, 2004. Proceedings. 5th International Symposium on; 02/2004
- 01/1990; Computer Science Press., ISBN: 978-0-7167-8179-0