Conference Proceeding

A High Speed CMOS Transmitter and Rail-to-Rail Receiver

Inst. of Comput. Technol., Beijing;
02/2008; DOI:10.1109/DELTA.2008.32 ISBN: 978-0-7695-3110-6 pp.67-70 In proceeding of: Electronic Design, Test and Applications, 2008. DELTA 2008. 4th IEEE International Symposium on
Source: IEEE Xplore

ABSTRACT This paper presents a high speed low voltage differential signal (LVDS) interface circuit for CPU, LCD, FPGA and other fast links. In the proposed transmitter a stable reference and a common mode feedback circuit are applied into the LVDS drivers, which enable the transmitter to tolerate the variations of process, temperature and supply voltage. The proposed receiver implements a rail-to-rail amplifier architecture which allows a 1.6 Gb/s transmission. The transmitter and receiver are implemented in HJ TC 3.3 v, 0.18 plusmn CMOS technology. Transmission operations up to 1.6 Gb/s with random data patterns were demonstrated. The transmitter and receiver pad cells exhibit a power consumption of 35 mW and 6 mW respectively.

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Keywords

0.18 plusmn CMOS technology
 
common mode feedback circuit
 
CPU
 
fast links
 
Gb/s transmission
 
paper presents
 
power consumption
 
rail-to-rail amplifier architecture
 
receiver pad cells exhibit
 
speed low voltage differential signal
 
supply voltage
 
Transmission operations
 
variations