Determination of Critical Parameters for Crosstalk Faults between On-chip Interconnects using Worst-Case Methods
ABSTRACT Interconnects being the limiting factor for both performance and density in today's VLSI systems, interconnect parasitics are considered to be the prime sources of signal integrity problems. Line inductance and/or mutual inductance in certain interconnect lines usually give rise to overshoots and undershoots in voltage waveforms which may cause reliability concerns in circuits, cause glitches and may lead to false transitions at the gate output. Therefore, it is important to track down the limiting values or the critical parameters of influential parameters below which a fault tolerant behavior of the device can be guaranteed. Earlier, there have been some analytical approaches for calculating these critical values, which are always prone to the availability of direct analytical equations for each and every case. In this paper, we explored a numerical based technique called the advanced worst-case method to track down the critical parameter set. The worst-case method taken up in this work is capable of accurately and efficiently calculating the critical values in diverse scenarios. The concept has been validated on a comprehensive distributed crosstalk fault model that considers RLGC parameters, coupling parameters together with the strengths of the driver and the receiver.
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ABSTRACT: This paper reflects on some recent results that show the value of delay-fault tests on a deep sub-micron process. However, the results also suggest that untargetted test patterns perform almost as well as those targetted on a transition fault model, despite appearing to have a much lower fault coverage. This leads to an examination of the defect mechanisms in deep sub-micron ICs, in particular the relationship of crosstalk and power-rail coupling to resistive opens and resistive bridges. A number of new fault mechanisms are described. The paper shows the importance of initialization conditions for resistive opens and the importance of noise margins with resistive bridges. These noise margin considerations throw doubts on the idea used by other authors of the “critical resistance” of a bridgeTest Conference, 2000. Proceedings. International; 02/2000
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ABSTRACT: The intricacy in the manufacturing of MEMS devices has resulted in decreasing parametric yields. The problem of reduced parametric yield is increasing with the waning feature sizes. The necessity for yield enhancement in MEMS designs and particularly in commercial MEMS is being increasingly felt by the industry and therefore by the designers. There has been no standard methodology that could be followed to enhance yield in the design phase. In this paper we undertake effort in order to standardize a best practice design method in order to achieve a better yield in the design phase. The method is still in its infancy and has good scope for development. The validity of the proposed method is demonstrated via a simulation based approach on a U-Shaped micro electro thermal actuator.Electronic Components and Technology Conference, 2007. ECTC '07. Proceedings. 57th; 07/2007
Conference Paper: Design for Reliability (DfR) in MEMS using Worst-Case Methods[Show abstract] [Hide abstract]
ABSTRACT: The growing applications of microsystem devices in extreme environments have a great impact on the rising importance of their reliability studies. Reliability study in MEMS lacks the availability of methods and tools to analyze them in a quick and efficient way. In this paper, we present a novel approach for reliability analysis in MEMS using worst-case methods. The method facilitates the designers to find out the critical operational parameters of the device with respect to a particular functional specification. This paper also introduces a reliability coefficient instigated from an inherent advantage of the worst-case methods.Physical and Failure Analysis of Integrated Circuits, 2007. IPFA 2007. 14th International Symposium on the; 08/2007