A Top-Down Design Verification Based on Reuse Modular and Parametric Behavioral Modeling for Subranging Pipelined Analog-to-Digital Converter
ABSTRACT This paper proposes a new approach to high speed pipelined A/D converter design. This technique combines a known subranging technique into pipelined architecture. A 8-bit 100 MSample/s subranging pipelined analog-to-digital converter (ADC) is implemented using this technique. The calibration techniques used are namely digital error correction, redundancy, and coarse and fine synchronization. To validate the proposed ADC, a top-down design methodology based on modular and parametric behavioral components is adopted. It supports a design process where non-ideal effects are incorporated in an incremental way, allowing easy architectural selection with fast and accurate simulations. The behavioral models are written in standard hardware description language, Verilog-AMS.
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ABSTRACT: Two-step flash architectures are an effective means of realizing high-speed high-resolution analog-to-digital converters (ADCs) because they can be implemented without the need for operational amplifiers having either high gain or a large output swing. Moreover, with conversion rates approaching half those of fully parallel designs, such half-flash architectures provide both a relatively small input capacitance and low power dissipation. The authors describe the design of a 12-b 5-Msample/s A/D converter that is based on a two-step flash topology and has been integrated in a 1-μm CMOS technology. Configured as a fully differential circuit, the converter performs a 7-b coarse flash conversion followed by a 6-b fine flash conversion. Both analog and digital error correction are used to achieve a resolution of 12 b. The converter dissipates only 200 mW from a single 5-V supply and occupies an area of 2.5 mm × 3.7 mmIEEE Journal of Solid-State Circuits 01/1993; 27(12-27):1667 - 1678. DOI:10.1109/4.173092 · 3.11 Impact Factor
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ABSTRACT: This paper describes a 10 b, 20 Msample/s pipeline A/D converter implemented in 1.2 μm CMOS technology which achieves a power dissipation of 35 mW at full speed operation. Circuit techniques used to achieve this level of power dissipation include digital correction to allow the use of dynamic comparators, and optimum scaling of capacitor values through the pipeline. Also, to be compatible with low voltage mixed-signal system environments, a switched capacitor (SC) circuit in each pipeline stage is implemented and operated at 3.3 V with a new high-speed, low-voltage operational amplifier and charge pump circuits. Measured performance includes 0.6 LSB of INL, 59.1 dB of SNDR (Signal-to-Noise-plus-Distortion-Ratio) for 100 kHz input at 20 Msample/s. At Nyquist sampling (10 MHz input) SNDR is 55.0 dB. Differential input range is ±1 V, and measured input referred RMS noise is 220 μV. The power dissipation at 1 MS/s is below 3 mW with 58 dB of SNDRIEEE Journal of Solid-State Circuits 04/1995; 30(3-30):166 - 172. DOI:10.1109/4.364429 · 3.11 Impact Factor
Article: Full-speed testing of A/D converters[Show abstract] [Hide abstract]
ABSTRACT: Improved computer-aided analog-to-digital converter (ADC) characterization methods based on the code density test and spectral analysis using the fast Fourier transform are described. The code density test produces a histogram of the digital output codes of an ADC sampling a known input. The code density can be interpreted to compute the differential and integral nonlinearities, gain error, offset error, and internal noise. Conversion-rate and frequency-dependent behavior can also be measured.IEEE Journal of Solid-State Circuits 01/1985; DOI:10.1109/JSSC.1984.1052232 · 3.11 Impact Factor