Conference Proceeding

A 26.5–37.5 GHz frequency divider and a 73-GHz-BW CML buffer in 0.13μm CMOS

Seoul Nat. Univ., Seoul
12/2007; DOI:10.1109/ASSCC.2007.4425752 ISBN: 978-1-4244-1360-7 pp.148 - 151 In proceeding of: Solid-State Circuits Conference, 2007. ASSCC '07. IEEE Asian
Source: IEEE Xplore

ABSTRACT This paper presents a frequency divider with a wide operating frequency range and a high bandwidth CML buffer intended for an 80-Gb/s serial link system. The proposed divider uses a pulsed-latch architecture that replaces the slave latch in a flip-flop-based divider with a buffer. The CML buffer employs both shunt-and-double-series inductive peaking and active feedback. Implemented in a 0.13-mum CMOS process with fT of only 82 GHz, the divider operates over a wide range of 26.5-37.S GHz with an input sensitivity of 1 Vpp, diff and produces a nominal output swing of 1 Vpp, diff. The CML buffer achieves a -3 dB bandwidth of 73.5 GHz in simulation, which is high enough to buffer an 80-Gb/s NRZ data stream. The fabricated frequency divider and clock buffers dissipate 22.5 mW and 72 mW, respectively, from a 1.8-V supply.

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Keywords

80-Gb/s serial link system
 
active feedback
 
bandwidth CML buffer
 
buffer
 
clock buffers
 
CML buffer
 
divider
 
fabricated frequency divider
 
flip-flop-based divider
 
frequency divider
 
Implemented
 
input sensitivity
 
proposed divider
 
pulsed-latch architecture
 
shunt-and-double-series inductive peaking
 
wide
 
wide range
 

Jeong-Kyoum Kim