A 1 GHz OTA-based low-pass filter with a high-speed automatic tuning scheme
ABSTRACT A continuous-time 4th-order equiripple linear phase G m -C filter with an automatic tuning circuit is presented. A high speed OTA based on the inverter structure is realized. The combined CMFF and CMFB circuit ensures the input and output common-mode stability. The gain performance could be maintained by combining a negative resistor at the output nodes. Transconductance tuning can be achieved by adjusting the bulk voltage by using the Deep-NWELL technology. Through the use of the OTA as a building block with a modified automatic tuning scheme, the filter -3 dB cutoff frequency is 1 GHz with the group delay less than 4% variation up to 1.5 fc frequency. The -43 dB of IM3 at filter cutoff frequency is obtained with -4 dbm two tone signals. Implemented in 0.18-mum CMOS process, the chip occupies 1mm2 and consumes 175 mW at a 1.5-V supply voltage.
Conference Paper: A 100 MHz Gm-C bandpass filter chip design for wireless application[Show abstract] [Hide abstract]
ABSTRACT: A sixth-order Butterworth bandpass filter using a leap-frog Gm-C structure for wireless applications is proposed. The filter is targeted for an intermediate frequency (IF) receiver, which has a center frequency of 100 MHz and a passband of 20 MHz. Fully differential Nauta's transconductors are used in this design, allowing the circuit to work over a large frequency range. The single-to-differential converter before the filter is designed in order to provide differential output for filter usage. The proposed bandpass filter including converter has been fabricated in TSMC 0.35 urn CMOS process with 3.3 V supply voltage. Measured results show that the proposed Gm-C bandpass filter achieves a center frequency of 94.45 MHz and a passband of 25 MHz. The chip area including pads is only 0.475 mm2 and the power dissipation is 42.25 mW.Wireless Communications & Signal Processing (WCSP), 2012 International Conference on; 01/2012
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ABSTRACT: Linearity and intrinsic gain enhancement tech- niques for realizing high-performance and low-voltage analog circuits in a deep-submicron CMOS are introduced. In place of a differential amplifier for the voltage-to-current (V/I) conversion at the input, a V/I conversion using a linear resistor and a positive feedback in a pseudo-differential configuration was adopted. The positive feedback concept was also applied to enhance the intrinsic gain of the deep-submicron MOS transistor which is used as a current source to realize high output impedance in amplifiers. In order to verify the effectiveness of the proposed techniques, a MOS 7th-order Gm-C linear phase low-pass-filter (LPF) was realized using a 65-nm CMOS process. Evaluation results showed that the -3 dB frequency bandwidth, group delay ripple, 3rd-order distortion and 3rd-order input intercept point (IIP3) were 200 MHz, 2.2%, less than -55 dB with a 100-MHz input and +10.3 dBm, respectively, all with a §0.1 Vp-p signal input at each input terminal in pseudo differential configuration, while the LPF including an output buffer dissipated 60 mW from a 1.2-V supply.Proceedings of the 37th European Solid-State Circuits Conference, ESSCIRC 2011, Helsinki, Finland, Sept. 12-16, 2011; 01/2011
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ABSTRACT: A low-power, low-voltage CMOS fully differential operational transconductance amplifier (OTA) operating in weak inversion region is presented in this paper. The proposed element allows the use of very small current for low-power and low-voltage features. The performances are examined through PSPICE simulations, displaying usabilities of the new active element. The power consumption is about 221 nW at ±0.75 V and bias current I<sub>E</sub> is 50 nA. The description includes example as a balance output full-wave rectifier.Signal Processing Systems (ICSPS), 2010 2nd International Conference on; 08/2010