Conference Paper

A 1 GHz OTA-Based low-pass filter with a high-speed automatic tuning scheme

Nat. Chiao Tung Univ., Hsinchu
DOI: 10.1109/ASSCC.2007.4425717 Conference: Solid-State Circuits Conference, 2007. ASSCC '07. IEEE Asian
Source: IEEE Xplore


A continuous-time 4th-order equiripple linear phase G m -C filter with an automatic tuning circuit is presented. A high speed OTA based on the inverter structure is realized. The combined CMFF and CMFB circuit ensures the input and output common-mode stability. The gain performance could be maintained by combining a negative resistor at the output nodes. Transconductance tuning can be achieved by adjusting the bulk voltage by using the Deep-NWELL technology. Through the use of the OTA as a building block with a modified automatic tuning scheme, the filter -3 dB cutoff frequency is 1 GHz with the group delay less than 4% variation up to 1.5 fc frequency. The -43 dB of IM3 at filter cutoff frequency is obtained with -4 dbm two tone signals. Implemented in 0.18-mum CMOS process, the chip occupies 1mm2 and consumes 175 mW at a 1.5-V supply voltage.

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    ABSTRACT: A class-AB, dual path building block for Gm-C filter that has high linearity and high PSRR is presented. The class-AB action provides good linearity and gm/Id while the dual path approach solves the PSRR problem associated with conventional class-AB OTA. A current-mode 4<sup>th</sup> order Butterworth filter designed using the proposed building block in 0.13 mum CMOS technology provides 54.2 dB IM3 and 52 dB SNR in 1.3 GHz bandwidth while consuming as low as 24 mW. It occupies 0.1 mm<sup>2</sup>.
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    ABSTRACT: A 260 MHz continuous-time 5<sup>th</sup>-order Gm-C biquad low-pass filter with an automatic tuning circuit is described. The Nauta¿s transconductor is applied for high frequency design. The cutoff frequency tuning can be achieved by adjusting load capacitance in two ways. The filter cutoff frequency is 260 MHz. The HD<sub>3</sub> is less than -50 dB for input signals up to 400 mVpp. The power consumption is 24 mW with 1.8-V supply voltage.
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    ABSTRACT: A CMOS fourth-order linear phase low-pass filter used for high speed wireless/wireline system is realized in 0.18-¿m CMOS process. The high speed filter is designed based on operational transconductance amplifier (OTA) biquad sections. As well known, large transconductance is required for high speed applications, and thus the conventional source degeneration topology, which operates with the trade-off of linearity and transconductance, is not suitable. In this paper, the proposed OTA use the negative current feedback topology to maintain linearity for high speed application. By using the proposed OTA as a building block, a 4-th order low-pass filter is realized. Fabricating in 0.18-¿m CMOS technology, the -3 dB filter frequency response at 250 MHz is measured. The measured HD3 performance is about -40 dB and the group delay variation is less than 5 ns at the filter -3 dB cutoff frequency.
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